Patents by Inventor Kazuo Nojiri

Kazuo Nojiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6036816
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 14, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Kojima, Yoshimi Torii, Michimasa Hunabashi, Kazuyuki Suko, Takashi Yamada, Keizo Kuroiwa, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
  • Patent number: 5952245
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yoshimi Torii, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
  • Patent number: 5917211
    Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 29, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
  • Patent number: 5868854
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
    Type: Grant
    Filed: December 8, 1992
    Date of Patent: February 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Kojima, Yoshimi Torii, Michimasa Hunabashi, Kazuyuki Suko, Takashi Yamada, Keizo Kuroiwa, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
  • Patent number: 5822081
    Abstract: A facsimile apparatus having a casing with a handset arranged on one side of the casing. The network control section is disposed adjacent to the handset within the casing. The power supply section is disposed within but on an opposite side of the casing as the network control section so as to avoid the electromagnetic interference by components of the power supply section with components of the network control section.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 13, 1998
    Assignee: Matsushita Graphic Communication Systems, Inc.
    Inventors: Yasuhiro Hatano, Hajime Takayama, Yasushi Fukada, Kazuhiko Kurita, Kazuo Nojiri
  • Patent number: 5734188
    Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
  • Patent number: 5661061
    Abstract: A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: August 26, 1997
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corporation
    Inventors: Hirohisa Usuami, Kazuyuki Tsunokuni, Masayuki Kojima, Kazuo Nojiri, Keiji Okamoto
  • Patent number: 5646489
    Abstract: A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: July 8, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Kakehi, Yoshinao Kawasaki, Keizo Suzuki, Kazuo Nojiri, Hiromichi Enami, Tetsunori Kaji, Seiichi Watanabe, Yoshifumi Ogawa
  • Patent number: 5568277
    Abstract: The facsimile apparatus includes a casing with a handset arranged on a side thereof. Within the casing are disposed a network control section adjacent the handset and a power supply section opposite the network control section. A control board is arranged above the network control and power supply sections. The control board includes an analog signal control section adjacent to the network control section, a driving control section adjacent to the power supply section for driving a preselected electrical part, and a digital signal control section between the analog signal control section and the driving control section.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: October 22, 1996
    Assignee: Matsushita Graphic Communication Systems, Inc.
    Inventors: Yasuhiro Hatano, Hajime Takayama, Yasushi Fukada, Kazuhiko Kurita, Kazuo Nojiri
  • Patent number: 5452110
    Abstract: A facsimile apparatus is provided which includes a casing, a system control unit for controlling a facsimile operation, an optical system, reading facsimile data of a transmit document, arranged below the system control unit within the casing, and a document feeding path, provided above the system control unit, for feeding the transmit document to a reading station where the optical system reads the facsimile data of the transmit document. These arrangements provide a compact structure of the facsimile apparatus.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: September 19, 1995
    Assignee: Matsushita Graphic Communication Systems, Inc.
    Inventors: Yasuhiro Hatano, Hajime Takayama, Yasushi Fukada, Kazuhiko Kurita, Kazuo Nojiri
  • Patent number: 5433789
    Abstract: A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically-conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: July 18, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Kakehi, Yoshinao Kawasaki, Keizo Suzuki, Kazuo Nojiri, Hiromichi Enami, Tetsunori Kaji, Seiichi Watanabe, Yoshifumi Ogawa
  • Patent number: 5264712
    Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
    Type: Grant
    Filed: May 7, 1992
    Date of Patent: November 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
  • Patent number: 5200017
    Abstract: A method of processing a sample comprises etching the sample by means of an etching plasma, and then treating the sample by means of a second plasma to remove residual corrosive compounds formed by the etching plasma. Removal of the residual corrosive compounds and prevention of corrosion is much improved by contacting the surface of the sample after the second plasma treatment with at least one liquid in order to effect at least one of (a) removal of the residual corrosive compounds and (b) passivation of the surface, and drying the sample.
    Type: Grant
    Filed: January 7, 1991
    Date of Patent: April 6, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinao Kawasaki, Hironobu Kawahara, Yoshiaki Sato, Ryooji Fukuyama, Kazuo Nojiri, Yoshimi Torii
  • Patent number: 5007981
    Abstract: A sample is plasma etched and then treated with a second plasma to remove residual corrosive compounds formed by the etching plasma. Removal of the residual corrosive compounds and prevention of corrosion is improved by washing the surface of the sample after the second plasma treatment with at least one liquid in order to effect at least one of (a) removal of the residual corrosive compounds and (b) passivation of the surface, the step of washing is followed by drying the sample.
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: April 16, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinao Kawasaki, Hironobu Kawahara, Yoshiaki Sato, Ryooji Fukuyama, Kazuo Nojiri, Yoshimi Torii