Patents by Inventor Kazuyoshi Muraoka
Kazuyoshi Muraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240071478Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Applicant: Kioxia CorporationInventors: Hideyuki KATAOKA, Yoshinao SUZUKI, Mai SHIMIZU, Kazuyoshi MURAOKA, Masami MASUDA, Yoshikazu HOSOMURA
-
Publication number: 20230083392Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.Type: ApplicationFiled: February 24, 2022Publication date: March 16, 2023Inventors: Yoshikazu HOSOMURA, Hideyuki KATAOKA, Yoshinao SUZUKI, Mai SHIMIZU, Kazuyoshi MURAOKA, Masami MASUDA
-
Patent number: 10431266Abstract: A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.Type: GrantFiled: August 6, 2018Date of Patent: October 1, 2019Assignee: Toshiba Memory CorporationInventors: Kazuyoshi Muraoka, Masami Masuda, Junya Matsuno, Masatoshi Kohno, Yuui Shimizu
-
Patent number: 10340857Abstract: According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.Type: GrantFiled: September 8, 2017Date of Patent: July 2, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junya Matsuno, Kazuyoshi Muraoka, Masami Masuda, Yuui Shimizu, Masatoshi Kohno, Masahiro Hosoya
-
Publication number: 20190088294Abstract: A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.Type: ApplicationFiled: August 6, 2018Publication date: March 21, 2019Inventors: Kazuyoshi MURAOKA, Masami MASUDA, Junya MATSUNO, Masatoshi KOHNO, Yuui SHIMIZU
-
Publication number: 20180254750Abstract: According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.Type: ApplicationFiled: September 8, 2017Publication date: September 6, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Junya MATSUNO, Kazuyoshi MURAOKA, Masami MASUDA, Yuui SHIMIZU, Masatoshi KOHNO, Masahiro HOSOYA
-
Patent number: 8189424Abstract: A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.Type: GrantFiled: March 4, 2009Date of Patent: May 29, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazuto Uehara, Toshifumi Watanabe, Shigefumi Ishiguro, Kazuyoshi Muraoka
-
Publication number: 20090316494Abstract: A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.Type: ApplicationFiled: March 4, 2009Publication date: December 24, 2009Inventors: Kazuto UEHARA, Toshifumi Watanabe, Shigefumi Ishiguro, Kazuyoshi Muraoka
-
Patent number: 7177210Abstract: A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.Type: GrantFiled: March 1, 2006Date of Patent: February 13, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Hamada, Kazuyoshi Muraoka, Masahiro Yoshihara
-
Publication number: 20060146620Abstract: A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.Type: ApplicationFiled: March 1, 2006Publication date: July 6, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Makoto Hamada, Kazuyoshi Muraoka, Masahiro Yoshihara
-
Patent number: 7038969Abstract: A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.Type: GrantFiled: September 15, 2004Date of Patent: May 2, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Hamada, Kazuyoshi Muraoka, Masahiro Yoshihara
-
Publication number: 20050088874Abstract: A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.Type: ApplicationFiled: September 15, 2004Publication date: April 28, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto Hamada, Kazuyoshi Muraoka, Masahiro Yoshihara
-
Patent number: 6680873Abstract: The output terminal of a voltage generation circuit is connected to one end portion of a fuse circuit. A transistor is connected to the other end portion of the fuse circuit. In program mode, a voltage generated from the voltage generation circuit is applied to the fuse circuit and a current flows through the fuse circuit and the transistor. In verify mode, a current generated from the voltage generation circuit flows into a pad through a selected fuse circuit and a detection circuit.Type: GrantFiled: January 8, 2002Date of Patent: January 20, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Muraoka, Eiji Kozuka
-
Publication number: 20020093867Abstract: The output terminal of a voltage generation circuit is connected to one end portion of a fuse circuit. A transistor is connected to the other end portion of the fuse circuit. In program mode, a voltage generated from the voltage generation circuit is applied to the fuse circuit and a current flows through the fuse circuit and the transistor. In verify mode, a current generated from the voltage generation circuit flows into a pad through a selected fuse circuit and a detection circuit.Type: ApplicationFiled: January 8, 2002Publication date: July 18, 2002Inventors: Kazuyoshi Muraoka, Eiji Kozuka
-
Patent number: 6169699Abstract: There is provided a multi-bank-structured DRAM capable of high-speed data transfer without enlarging the chip size due to increase of the line width of power source lines and addition of internal power source generation circuits. In a multi-bank-structured DRAM, cell array units forming each bank are assigned divisionally to cell array units in both sides of an interface circuit interposed therebetween. This division of cell array units is carried out such that those units that are positioned point-symmetrically with respect to the center of the interface circuit are selected and are assigned to one same bank. As a result, the layout of internal power source circuits in the interface circuit can be designed in match with half of power dissipation of the chip. The line width of power source lines can therefore be reduced to small.Type: GrantFiled: December 21, 1999Date of Patent: January 2, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Kazuyoshi Muraoka
-
Patent number: 6126915Abstract: Titanium dioxide powder with a greatly decreased volatile moisture content can be obtained by surface treating with titanium dioxide powder with addition of a calcium salt and/or a silane coupling agent, or by a surface treatment by addition of an aluminate together with these surface treatments. A masterbatch containing this titanium dioxide powder is of high quality, having no defect due to foam generation upon high temperature processing.Type: GrantFiled: August 26, 1998Date of Patent: October 3, 2000Assignees: Tohkem Products Corporation, Toyo Ink Manufacturing Co., Ltd.Inventors: Makoto Tunashima, Kazuyoshi Muraoka, Kohji Yamamoto, Susumu Miyasita, Noburu Sakuma, Masaru Hosokawa
-
Patent number: 6113873Abstract: To hydrous titanium dioxide obtained by hydrolysis of titanium sulfate was added a predetermined amount of a water-soluble aluminum compound and/or a water-soluble zinc compound, the mixture is calcined, and a suitable amount of aluminum and/or zinc is introduced into the crystals to make up the crystal defects of anatase-type titanium dioxide, so that it has increased stability and excellent color stability.Type: GrantFiled: July 29, 1998Date of Patent: September 5, 2000Assignee: Sakai Chemical Industry Co., Ltd.Inventors: Makoto Tunashima, Kazuyoshi Muraoka, Kohji Yamamoto, Masaru Mikami, Suzuo Sasaki
-
Patent number: 5848011Abstract: A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal.Type: GrantFiled: March 26, 1997Date of Patent: December 8, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Muraoka, Masaru Koyanagi, Yoshiaki Takeuchi
-
Patent number: 5831421Abstract: A semiconductor device includes an internal circuit and first and second supply voltage-lowering circuits in its semiconductor chip. The first supply voltage-lowering circuit steps down an external power supply potential of the semiconductor chip in response to a control signal, generates a first internal power supply potential, and supplies it to the internal circuit. The second supply voltage-lowering circuit steps down the external power supply potential of the semiconductor chip in response to the control signal, generates a second internal power supply potential of substantially the same level as that of the first internal power supply potential, and supplies it to the internal circuit. The first and second internal power supply potentials output from the first and second supply voltage-lowering circuits vary out of phase with each other to cancel out variations in first and second internal power supply potentials.Type: GrantFiled: April 18, 1997Date of Patent: November 3, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Taira, Kazuyoshi Muraoka
-
Patent number: 5813210Abstract: A twisting frame 1, and a method of twisting yarn 11 in which a twist is applied to the yarn by signals having a 1/f fluctuation to yield a yarn 11 in which the yarn count varies with a 1/f fluctuation. The first aspect is a twisting method that applies twist to a single yarn or a plural number of yarns, in which a twist is applied to the yarn or yarns by setting the twist count to correspond to the strengths of serial signals having a 1/f fluctuation.Type: GrantFiled: May 9, 1997Date of Patent: September 29, 1998Assignees: Toshimitsu Musha, Nisshinbo Industries Inc.Inventors: Toshimitsu Musha, Yuichi Yanai, Kazuyoshi Muraoka, Yuki Niwa, Yasuo Nakano