Patents by Inventor Ke-Hung Chen
Ke-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210327881Abstract: Some embodiments include an integrated assembly having capacitor-contact-regions. Metal-containing interconnects are coupled with the capacitor-contact-regions. A first insulative material is between the metal-containing interconnects. A second insulative material is over the first insulative material. A third insulative material is over the second insulative material. First capacitor electrodes extend through the second and third insulative materials and are coupled with the metal-containing interconnects. Fourth insulative material is adjacent the first capacitor electrodes. Capacitor plate electrodes are adjacent the fourth insulative material and are spaced from the first capacitor electrodes by the fourth insulative material. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Ke-Hung Chen, Christopher W. Petz, Pankaj Sharma, Yong Mo Yang
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Patent number: 10436717Abstract: Described herein are architectures, platforms and methods for detecting and analyzing anomalous events (i.e., arcing events) from spectral data gathered during a wafer fabrication process.Type: GrantFiled: November 17, 2017Date of Patent: October 8, 2019Assignee: Tokyo Electron LimitedInventors: Thomas Omstead, Ke-Hung Chen, Deepak Vedhachalam
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Publication number: 20180143141Abstract: Described herein are architectures, platforms and methods for detecting and analyzing anomalous events (i.e., arcing events) from spectral data gathered during a wafer fabrication process.Type: ApplicationFiled: November 17, 2017Publication date: May 24, 2018Inventors: Thomas Omstead, Ke-Hung Chen, Deepak Vedhachalam
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Patent number: 8884433Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.Type: GrantFiled: August 24, 2009Date of Patent: November 11, 2014Assignee: Qualcomm IncorporatedInventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
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Patent number: 8558383Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.Type: GrantFiled: November 4, 2008Date of Patent: October 15, 2013Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
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Patent number: 8399989Abstract: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.Type: GrantFiled: July 31, 2006Date of Patent: March 19, 2013Assignee: Megica CorporationInventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
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Patent number: 8304766Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.Type: GrantFiled: April 26, 2011Date of Patent: November 6, 2012Assignee: Megica CorporationInventors: Mou-Shiung Lin, Huei-Mei Yen, Hsin-Jung Lo, Chiu-Ming Chou, Ke-Hung Chen
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Patent number: 8294279Abstract: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.Type: GrantFiled: January 24, 2006Date of Patent: October 23, 2012Assignee: Megica CorporationInventors: Ke-Hung Chen, Shih-Hsiung Lin, Mou-Shiung Lin
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Patent number: 8148822Abstract: A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.Type: GrantFiled: May 17, 2006Date of Patent: April 3, 2012Assignee: Megica CorporationInventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
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Publication number: 20110198589Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.Type: ApplicationFiled: April 26, 2011Publication date: August 18, 2011Applicant: Megica CorporationInventors: Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Hsin-Jung Lo, Ke-Hung Chen
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Patent number: 7947978Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.Type: GrantFiled: December 5, 2006Date of Patent: May 24, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Hsin-Jung Lo, Ke-Hung Chen
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Publication number: 20090309224Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.Type: ApplicationFiled: August 24, 2009Publication date: December 17, 2009Applicant: MEGICA CORPPORATIONInventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
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Patent number: 7582556Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.Type: GrantFiled: June 26, 2006Date of Patent: September 1, 2009Assignee: MEGICA CorporationInventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
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Publication number: 20090057895Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.Type: ApplicationFiled: November 4, 2008Publication date: March 5, 2009Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
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Patent number: 7468545Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.Type: GrantFiled: May 8, 2006Date of Patent: December 23, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
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Publication number: 20070164279Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.Type: ApplicationFiled: December 5, 2006Publication date: July 19, 2007Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Hsin-Jung Lo, Ke-Hung Chen
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Publication number: 20070026631Abstract: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.Type: ApplicationFiled: July 31, 2006Publication date: February 1, 2007Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
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Publication number: 20070023919Abstract: A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.Type: ApplicationFiled: May 17, 2006Publication date: February 1, 2007Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
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Publication number: 20060292851Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.Type: ApplicationFiled: June 26, 2006Publication date: December 28, 2006Inventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
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Publication number: 20060291029Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.Type: ApplicationFiled: May 8, 2006Publication date: December 28, 2006Inventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen