Patents by Inventor Keiichi Tanabe
Keiichi Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7505310Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.Type: GrantFiled: March 14, 2006Date of Patent: March 17, 2009Assignee: NEC CorporationInventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe
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Patent number: 7378865Abstract: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second pulse generating circuit to produce a single flux quantum pulse responsive to the second alternating-current output, and a confluence buffer circuit to merge the single flux quantum pulses from the pulse generating circuits, wherein each of the pulse generating circuits includes a superconducting loop including the secondary-side inductor, a first Josephson junction situated in the superconducting loop to generate the single flux quantum pulse, and a second Josephson junction situated in the superconducting loop, a threshold value of the second Josephson junction for an electric current flowing through the secondary-side inductor being different from thaType: GrantFiled: September 1, 2006Date of Patent: May 27, 2008Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical FoundationInventors: Atsushi Taguchi, Takuya Himi, Hideo Suzuki, Akira Yoshida, Keiichi Tanabe
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Publication number: 20080051292Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
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Patent number: 7323711Abstract: A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the second electrode layer (6) is greater than the width of the first electrode layer (5). The first electrode layer (5) and the second electrode layer (6) touch in part, and are separated via a first insulation layer (7) in remaining part. Because the ramp-edge junction includes the first electrode layer (5) and the second electrode layer (6), the inductance of the ramp-edge junction can be reduced with the critical current density Jc being kept at a high level.Type: GrantFiled: July 27, 2004Date of Patent: January 29, 2008Assignees: FUJITSU Limited, International Superconductivity Technology Center, the Juridical FoundationInventors: Hideo Suzuki, Masahiro Horibe, Keiichi Tanabe
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Publication number: 20070281861Abstract: The present invention provides a superconducting device including a substrate, a first superconducting pattern formed on the substrate, an insulating pattern formed on the first superconducting pattern, and a second superconducting pattern formed at the uppermost level in the multilayered superconducting pattern. A barrier layer of a Josephson junction is formed on the lower side of, or within the second superconducting pattern. The second superconducting pattern constitutes a circuit element on the insulating pattern.Type: ApplicationFiled: May 30, 2007Publication date: December 6, 2007Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATIONInventors: Yoshihiro Ishimaru, Yoshinobu Tarutani, Keiichi Tanabe
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Patent number: 7300909Abstract: A first Josephson junction in a Single Flux Quantum circuit (SFQ circuit) and a second Josephson junction in an interface circuit (latch driver circuit) are formed with junction materials different from each other, and the junction materials are selected so that the hysteresis of the first Josephson junction in a current-voltage characteristic is smaller than the hysteresis of the second Josephson junction in a current-voltage characteristic.Type: GrantFiled: March 26, 2004Date of Patent: November 27, 2007Assignee: Fujitsu LimitedInventors: Tsunehiro Hato, Masahiro Horibe, Keiichi Tanabe
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Patent number: 7268713Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.Type: GrantFiled: September 21, 2006Date of Patent: September 11, 2007Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical FoundationInventors: Hideo Suzuki, Keiichi Tanabe
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Publication number: 20070158791Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.Type: ApplicationFiled: October 20, 2006Publication date: July 12, 2007Inventors: Hironori Wakana, Koji Tsubone, Yoshinobu Tarutani, Yoshihiro Ishimaru, Keiichi Tanabe
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Publication number: 20070052441Abstract: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second pulse generating circuit to produce a single flux quantum pulse responsive to the second alternating-current output, and a confluence buffer circuit to merge the single flux quantum pulses from the pulse generating circuits, wherein each of the pulse generating circuits includes a superconducting loop including the secondary-side inductor, a first Josephson junction situated in the superconducting loop to generate the single flux quantum pulse, and a second Josephson junction situated in the superconducting loop, a threshold value of the second Josephson junction for an electric current flowing through the secondary-side inductor being different from thaType: ApplicationFiled: September 1, 2006Publication date: March 8, 2007Applicants: FUJITSU LIMITED,, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION,Inventors: Atsushi Taguchi, Takuya Himi, Hideo Suzuki, Akira Yoshida, Keiichi Tanabe
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Publication number: 20070049097Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.Type: ApplicationFiled: September 21, 2006Publication date: March 1, 2007Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATIONInventors: Satoru Hirano, Hideo Suzuki, Keiichi Tanabe, Akira Yoshida, Tsunehiro Hato, Michitaka Maruyama
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Publication number: 20060255987Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.Type: ApplicationFiled: March 14, 2006Publication date: November 16, 2006Inventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe
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Publication number: 20060247131Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.Type: ApplicationFiled: January 13, 2006Publication date: November 2, 2006Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATIONInventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
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Patent number: 7129870Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.Type: GrantFiled: August 27, 2004Date of Patent: October 31, 2006Assignees: Fujitsu Limited, International SuperConductivity Technology Center, The Juridical FoundationInventors: Satoru Hirano, Hideo Suzuki, Keiichi Tanabe, Akira Yoshida, Tsunehiro Hato, Michitaka Maruyama
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Patent number: 7095227Abstract: To obtain a superconducting driver circuit which can obtain an output voltage of several millvolts or above, can use a DC power source as a driving power source, can form no capacitance between it and a ground plane, and has a small occupation area, the superconducting driver circuit is constructed by superconducting flux quantum interference devices (SQUIDs) each constructing a closed loop having as components two superconducting junctions and an inductor. The SQUIDs share the inductors and are connected in series in three or more stages.Type: GrantFiled: August 5, 2003Date of Patent: August 22, 2006Assignee: International Superconductivity Technology Center, the Juridical FoundationInventors: Yoshinobu Tarutani, Masahiro Horibe, Keiichi Tanabe
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Patent number: 7091515Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.Type: GrantFiled: March 26, 2004Date of Patent: August 15, 2006Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical FoundationInventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
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Patent number: 7081417Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.Type: GrantFiled: June 24, 2004Date of Patent: July 25, 2006Assignees: Hitachi, Ltd., NEC Corporation, International Superconductivity Technology Center, the Judicial FoundationInventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
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Patent number: 7038604Abstract: There is provided a superconducting multi-stage sigma-delta modulator including a first superconducting sigma-delta modulator having a first integrator and a first comparator and outputting a sigma-delta modulated signal and a second superconducting sigma-delta modulator having a second integrator and a second comparator and outputting a sigma-delta modulated signal. The first integrator and the second integrator are magnetically coupled.Type: GrantFiled: May 13, 2005Date of Patent: May 2, 2006Assignee: Fujitsu LimitedInventors: Satoru Hirano, Akira Yoshida, Sinya Hasuo, Keiichi Tanabe
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Patent number: 6999806Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.Type: GrantFiled: August 16, 2002Date of Patent: February 14, 2006Assignee: International Superconductivity Technology Center, the Juridical FoundationInventors: Seiji Adachi, Hironori Wakana, Keiichi Tanabe
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Publication number: 20050253746Abstract: There is provided a superconducting multi-stage sigma-delta modulator including a first superconducting sigma-delta modulator having a first integrator and a first comparator and outputting a sigma-delta modulated signal and a second superconducting sigma-delta modulator having a second integrator and a second comparator and outputting a sigma-delta modulated signal. The first integrator and the second integrator are magnetically coupled.Type: ApplicationFiled: May 13, 2005Publication date: November 17, 2005Inventors: Satoru Hirano, Akira Yoshida, Sinya Hasuo, Keiichi Tanabe
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Publication number: 20050231196Abstract: To obtain a superconducting driver circuit which can obtain an output voltage of several millvolts or above, can use a DC power source as a driving power source, can form no capacitance between it and a ground plane, and has a small occupation area, the superconducting driver circuit is constructed by superconducting flux quantum interference devices (SQUIDs) each constructing a closed loop having as components two superconducting junctions and an inductor. The SQUIDs share the inductors and are connected in series in three or more stages.Type: ApplicationFiled: August 5, 2003Publication date: October 20, 2005Inventors: Yoshinobu Tarutani, Masahiro Horibe, Keiichi Tanabe