Patents by Inventor Keiichi Tanabe

Keiichi Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7505310
    Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: March 17, 2009
    Assignee: NEC Corporation
    Inventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe
  • Patent number: 7378865
    Abstract: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second pulse generating circuit to produce a single flux quantum pulse responsive to the second alternating-current output, and a confluence buffer circuit to merge the single flux quantum pulses from the pulse generating circuits, wherein each of the pulse generating circuits includes a superconducting loop including the secondary-side inductor, a first Josephson junction situated in the superconducting loop to generate the single flux quantum pulse, and a second Josephson junction situated in the superconducting loop, a threshold value of the second Josephson junction for an electric current flowing through the secondary-side inductor being different from tha
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: May 27, 2008
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Atsushi Taguchi, Takuya Himi, Hideo Suzuki, Akira Yoshida, Keiichi Tanabe
  • Publication number: 20080051292
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 28, 2008
    Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Patent number: 7323711
    Abstract: A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the second electrode layer (6) is greater than the width of the first electrode layer (5). The first electrode layer (5) and the second electrode layer (6) touch in part, and are separated via a first insulation layer (7) in remaining part. Because the ramp-edge junction includes the first electrode layer (5) and the second electrode layer (6), the inductance of the ramp-edge junction can be reduced with the critical current density Jc being kept at a high level.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: January 29, 2008
    Assignees: FUJITSU Limited, International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Hideo Suzuki, Masahiro Horibe, Keiichi Tanabe
  • Publication number: 20070281861
    Abstract: The present invention provides a superconducting device including a substrate, a first superconducting pattern formed on the substrate, an insulating pattern formed on the first superconducting pattern, and a second superconducting pattern formed at the uppermost level in the multilayered superconducting pattern. A barrier layer of a Josephson junction is formed on the lower side of, or within the second superconducting pattern. The second superconducting pattern constitutes a circuit element on the insulating pattern.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 6, 2007
    Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION
    Inventors: Yoshihiro Ishimaru, Yoshinobu Tarutani, Keiichi Tanabe
  • Patent number: 7300909
    Abstract: A first Josephson junction in a Single Flux Quantum circuit (SFQ circuit) and a second Josephson junction in an interface circuit (latch driver circuit) are formed with junction materials different from each other, and the junction materials are selected so that the hysteresis of the first Josephson junction in a current-voltage characteristic is smaller than the hysteresis of the second Josephson junction in a current-voltage characteristic.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: November 27, 2007
    Assignee: Fujitsu Limited
    Inventors: Tsunehiro Hato, Masahiro Horibe, Keiichi Tanabe
  • Patent number: 7268713
    Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: September 11, 2007
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Hideo Suzuki, Keiichi Tanabe
  • Publication number: 20070158791
    Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.
    Type: Application
    Filed: October 20, 2006
    Publication date: July 12, 2007
    Inventors: Hironori Wakana, Koji Tsubone, Yoshinobu Tarutani, Yoshihiro Ishimaru, Keiichi Tanabe
  • Publication number: 20070052441
    Abstract: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second pulse generating circuit to produce a single flux quantum pulse responsive to the second alternating-current output, and a confluence buffer circuit to merge the single flux quantum pulses from the pulse generating circuits, wherein each of the pulse generating circuits includes a superconducting loop including the secondary-side inductor, a first Josephson junction situated in the superconducting loop to generate the single flux quantum pulse, and a second Josephson junction situated in the superconducting loop, a threshold value of the second Josephson junction for an electric current flowing through the secondary-side inductor being different from tha
    Type: Application
    Filed: September 1, 2006
    Publication date: March 8, 2007
    Applicants: FUJITSU LIMITED,, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION,
    Inventors: Atsushi Taguchi, Takuya Himi, Hideo Suzuki, Akira Yoshida, Keiichi Tanabe
  • Publication number: 20070049097
    Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 1, 2007
    Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION
    Inventors: Satoru Hirano, Hideo Suzuki, Keiichi Tanabe, Akira Yoshida, Tsunehiro Hato, Michitaka Maruyama
  • Publication number: 20060255987
    Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.
    Type: Application
    Filed: March 14, 2006
    Publication date: November 16, 2006
    Inventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe
  • Publication number: 20060247131
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Application
    Filed: January 13, 2006
    Publication date: November 2, 2006
    Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 7129870
    Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: October 31, 2006
    Assignees: Fujitsu Limited, International SuperConductivity Technology Center, The Juridical Foundation
    Inventors: Satoru Hirano, Hideo Suzuki, Keiichi Tanabe, Akira Yoshida, Tsunehiro Hato, Michitaka Maruyama
  • Patent number: 7095227
    Abstract: To obtain a superconducting driver circuit which can obtain an output voltage of several millvolts or above, can use a DC power source as a driving power source, can form no capacitance between it and a ground plane, and has a small occupation area, the superconducting driver circuit is constructed by superconducting flux quantum interference devices (SQUIDs) each constructing a closed loop having as components two superconducting junctions and an inductor. The SQUIDs share the inductors and are connected in series in three or more stages.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: August 22, 2006
    Assignee: International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Yoshinobu Tarutani, Masahiro Horibe, Keiichi Tanabe
  • Patent number: 7091515
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: August 15, 2006
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 7081417
    Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: July 25, 2006
    Assignees: Hitachi, Ltd., NEC Corporation, International Superconductivity Technology Center, the Judicial Foundation
    Inventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
  • Patent number: 7038604
    Abstract: There is provided a superconducting multi-stage sigma-delta modulator including a first superconducting sigma-delta modulator having a first integrator and a first comparator and outputting a sigma-delta modulated signal and a second superconducting sigma-delta modulator having a second integrator and a second comparator and outputting a sigma-delta modulated signal. The first integrator and the second integrator are magnetically coupled.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: May 2, 2006
    Assignee: Fujitsu Limited
    Inventors: Satoru Hirano, Akira Yoshida, Sinya Hasuo, Keiichi Tanabe
  • Patent number: 6999806
    Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: February 14, 2006
    Assignee: International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Keiichi Tanabe
  • Publication number: 20050253746
    Abstract: There is provided a superconducting multi-stage sigma-delta modulator including a first superconducting sigma-delta modulator having a first integrator and a first comparator and outputting a sigma-delta modulated signal and a second superconducting sigma-delta modulator having a second integrator and a second comparator and outputting a sigma-delta modulated signal. The first integrator and the second integrator are magnetically coupled.
    Type: Application
    Filed: May 13, 2005
    Publication date: November 17, 2005
    Inventors: Satoru Hirano, Akira Yoshida, Sinya Hasuo, Keiichi Tanabe
  • Publication number: 20050231196
    Abstract: To obtain a superconducting driver circuit which can obtain an output voltage of several millvolts or above, can use a DC power source as a driving power source, can form no capacitance between it and a ground plane, and has a small occupation area, the superconducting driver circuit is constructed by superconducting flux quantum interference devices (SQUIDs) each constructing a closed loop having as components two superconducting junctions and an inductor. The SQUIDs share the inductors and are connected in series in three or more stages.
    Type: Application
    Filed: August 5, 2003
    Publication date: October 20, 2005
    Inventors: Yoshinobu Tarutani, Masahiro Horibe, Keiichi Tanabe