Patents by Inventor Keiji Ishibashi

Keiji Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150221729
    Abstract: A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched between the first surface and the second surface. A plurality of grinding traces are formed in a surface of the peripheral edge portion. A chamfer width as a distance from an outermost peripheral end portion of the peripheral edge portion to one of the plurality of grinding traces which is located on an innermost peripheral side of the peripheral edge portion in a direction parallel to the first surface is not less than 50 ?m and not more than 400 ?m. Thereby, a silicon carbide single-crystal substrate capable of suppressing occurrence of a crack, and a method for manufacturing the same can be provided.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 6, 2015
    Inventors: Kyoko Okita, Keiji Ishibashi
  • Patent number: 9093384
    Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 28, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Keiji Ishibashi
  • Publication number: 20150194442
    Abstract: Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a group III-nitride-film-side main surface is 200 ?/sq or less.
    Type: Application
    Filed: September 4, 2013
    Publication date: July 9, 2015
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Yuki Hiromura, Naoki Matsumoto, Seiji Nakahata, Fumitake Nakanishi, Takuya Yanagisawa, Koji Uematsu, Yuki Seki, Yoshiyuki Yamamoto, Yusuke Yoshizumi, Hidenori Mikami
  • Patent number: 9070828
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 with a front surface 10a having a specific plane orientation. Accordingly, a high-resistivity layer is prevented from being formed at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Consequently, it is possible to improve the emission intensity of the semiconductor device 100.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: June 30, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Publication number: 20150162409
    Abstract: A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched between the first surface and the second surface. A plurality of grinding traces are formed in a surface of the peripheral edge portion. A chamfer width as a distance from an outermost peripheral end portion of the peripheral edge portion to one of the plurality of grinding traces which is located on an innermost peripheral side of the peripheral edge portion in a direction parallel to the first surface is not less than 50 ?m and not more than 400 ?m. Thereby, a silicon carbide single-crystal substrate capable of suppressing occurrence of a crack, and a method for manufacturing the same can be provided.
    Type: Application
    Filed: February 10, 2015
    Publication date: June 11, 2015
    Inventors: Kyoko Okita, Keiji Ishibashi
  • Publication number: 20150137319
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.
    Type: Application
    Filed: December 22, 2014
    Publication date: May 21, 2015
    Inventor: Keiji ISHIBASHI
  • Patent number: 9035429
    Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 19, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takayuki Nishiura, Keiji Ishibashi
  • Patent number: 8975643
    Abstract: A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched between the first surface and the second surface. A plurality of grinding traces are formed in a surface of the peripheral edge portion. A chamfer width as a distance from an outermost peripheral end portion of the peripheral edge portion to one of the plurality of grinding traces which is located on an innermost peripheral side of the peripheral edge portion in a direction parallel to the first surface is not less than 50 ?m and not more than 400 ?m. Thereby, a silicon carbide single-crystal substrate capable of suppressing occurrence of a crack, and a method for manufacturing the same can be provided.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kyoko Okita, Keiji Ishibashi
  • Patent number: 8952494
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Publication number: 20150008453
    Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Inventor: Keiji ISHIBASHI
  • Publication number: 20150008454
    Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Inventor: Keiji ISHIBASHI
  • Publication number: 20140367735
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 with a front surface 10a having a specific plane orientation. Accordingly, a high-resistivity layer is prevented from being formed at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Consequently, it is possible to improve the emission intensity of the semiconductor device 100.
    Type: Application
    Filed: September 3, 2014
    Publication date: December 18, 2014
    Inventor: Keiji Ishibashi
  • Publication number: 20140360863
    Abstract: The present invention provides a SrRuO3 film manufacturing method capable of depositing high-quality SrRuO3 film while achieving a high deposition rate and preventing occurrence of abnormal discharge in the process of depositing the SrRuO3 film by DC magnetron sputtering. An embodiment of the present invention is a SrRuO3 film deposition method by offset rotary deposition-type DC magnetron sputtering, which includes depositing SrRuO3 film on a substrate at a deposition pressure of 1.0 Pa or more and less than 8.0 Pa in an oxygen-containing atmosphere.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 11, 2014
    Inventors: Yoshiaki DAIGO, Keiji ISHIBASHI
  • Publication number: 20140349112
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Keiji ISHIBASHI, Tokiko KAJI, Seiji NAKAHATA, Takayuki NISHIURA
  • Patent number: 8871647
    Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Patent number: 8872189
    Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Patent number: 8853670
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 with a front surface 10a having a specific plane orientation. Accordingly, a high-resistivity layer is prevented from being formed at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Consequently, it is possible to improve the emission intensity of the semiconductor device 100.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 7, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Publication number: 20140291811
    Abstract: A group III nitride crystal substrate is provided in which a uniform distortion at a surface layer of the crystal substrate represented by a value of |d1?d2|/d2 obtained from a plane spacing d1 at the X-ray penetration depth of 0.3 ?m and a plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 1.9×10?3, and the main surface has a plane orientation inclined in the <10-10> direction at an angle equal to or greater than 10° and equal to or smaller than 80° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 2, 2014
    Inventors: Keiji ISHIBASHI, Yusuke YOSHIZUMI
  • Patent number: 8841215
    Abstract: Afforded are a polishing agent, and a compound semiconductor manufacturing method and semiconductor device manufacturing method utilizing the agent, whereby the surface quality of compound semiconductor substrates can be favorably maintained, and high polishing rates can be sustained as well. The polishing agent is a polishing agent for Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductors, and includes an alkali metal carbonate, an alkali metal organic salt, a chlorine-based oxidizer, and an alkali metal phosphate, wherein the sum of the concentrations of the alkali metal carbonate and the alkali metal organic salt is between 0.01 mol/L and 0.02 mol/L, inclusive. The compound semiconductor manufacturing method comprises a step of preparing a Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductor, and a step of polishing the face of the compound semiconductor utilizing an aforedescribed polishing agent.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 23, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Masashi Futamura, Takayuki Nishiura
  • Patent number: 8828140
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura