Patents by Inventor Keiji Tanaka

Keiji Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966115
    Abstract: Used is a display device including: a first substrate having a first front surface and a first back surface located on an opposite side of the first front surface; a second substrate having a second back surface opposing the first front surface and a second front surface located on an opposite side of the second back surface; a liquid crystal layer arranged between the first front surface of the first substrate and the second back surface of the second substrate; a first light guide plate adhesively fixed onto the second front surface of the second substrate via a first adhesive layer; and a light source unit arranged at a position opposing a first side surface of the first light guide plate, in which refractive index of the first light guide plate is lower than refractive index of the first adhesive layer.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: April 23, 2024
    Assignee: Japan Display Inc.
    Inventors: Yoshinori Tanaka, Keita Ono, Keiji Tago
  • Patent number: 11869399
    Abstract: A driving circuit includes first and second input signal terminals, first and second output signal terminals, constant current sources, first and second transistors having control terminals connected to the first and second input signal terminals, third and fourth transistors each having a control terminal to which a first bias voltage is applied, first and second inductors each having a first inductance, and third and fourth inductors each having a second inductance larger than the first inductance. The driving circuit further includes fifth and sixth transistors each having a control terminal to which a second bias voltage is applied, outflow terminals connected to inflow terminals of the third and fourth transistors via the first and second inductors, and inflow terminals connected to the first and second output signal terminals via the third and fourth inductors.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: January 9, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi Uemura, Keiji Tanaka
  • Publication number: 20230380056
    Abstract: A package for an optical module includes a substrate that includes a first wiring layer, a second wiring layer, and a third wiring layer. The package includes a first insulating layer between the first wiring layer and the second wiring layer, the first insulating layer including first vias. The package includes a second insulating layer between the second wiring layer and the third wiring layer, the second insulating layer including second vias and third vias. Each first vias is provided between a corresponding second via and a corresponding third via. The first vias are arranged at a first interval along a first direction. The second vias are arranged at a second interval along the first direction. Each second vias is disposed at an offset by half of the second interval from the corresponding third via.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 23, 2023
    Inventors: Taichi MISAWA, Keiji TANAKA
  • Publication number: 20230380057
    Abstract: A package for an optical module includes a substrate provided through a side wall in a first direction. The substrate includes a first wiring layer including a first signal terminal, a second signal terminal, and a first ground terminal. The package includes a second wiring layer disposed under the first wiring layer. The second wiring layer includes a first ground pattern and a first insulating layer disposed between the first wiring layer and the second wiring layer, and includes a groove extending along the first direction, the groove being filled with a metal. The groove is provided within the first ground terminal, in a plan view, and the first insulating layer is free of the groove. The first ground terminal is electrically coupled to the first ground pattern through the metal of the groove.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 23, 2023
    Inventors: Taichi MISAWA, Keiji TANAKA
  • Patent number: 11799288
    Abstract: An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a first node, a second diode circuit connected between the second output terminal and the first node, a first intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at a second node different from the first node, a first intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, a detection circuit configured to generate a trigger signal in accordance with the first intermediate voltage, and a switch circuit configured to electrically connect the first node to a ground line in accordance with the trigger signal.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 24, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi Uemura, Keiji Tanaka
  • Patent number: 11744008
    Abstract: A printed board includes a first wiring layer including a first terminal, a second wiring layer including a second terminal facing to the first terminal, a dielectric layer interposed between the first wiring layer and the second wiring layer and having an end face, and a plurality of through-hole vias configured to electrically connect the first terminal and the second terminal. The plurality of through-hole vias includes a first through-hole via which is closest to an end-face edge of the first terminal, and a second through-hole via which is closest to an inner edge of the second terminal. The end-face edge being closer to the end face than the inner edge. A distance between the first through-hole via and the end-face edge is equal to or smaller than one eighth of a signal wavelength of a high speed signal transmitted through the first terminal.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: August 29, 2023
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taichi Misawa, Keiji Tanaka
  • Publication number: 20230268895
    Abstract: An amplifier circuit includes a first cascode transistor and a second cascade transistor, the first cascade transistor being electrically connected between a first transistor and a first load circuit, the second cascode transistor being electrically connected between a second transistor and a second load circuit. The amplifier circuit includes a first shunt transistor and a second shunt transistor, the first shunt transistor being electrically connected between the first transistor and a first emitter-follower circuit, the second shunt transistor being electrically connected between the second transistor and a second emitter-follower circuit. A differential current signal includes a first differential current and a second differential current, the first differential current flowing through the first cascode transistor and the second cascode transistor, and a second differential current flowing through the first shunt transistor and the second shunt transistor.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 24, 2023
    Inventors: Taichi MISAWA, Keiji TANAKA
  • Publication number: 20230258698
    Abstract: An output circuit includes: an inductor, an amplifier circuit that outputs an output signal via the inductor, an output terminal that outputs the output signal to an outside, a voltage divider circuit including a series circuit constituted by a first capacitive element and a second capacitive element connected in series to the first capacitive element, the series circuit generating a first voltage-divided signal by dividing a voltage of the output signal, a first band-adjusting element having a resistance component for generating a first band-adjusted signal by adjusting frequency characteristics of the first voltage-divided signal, and a first peak detection circuit that detects a peak voltage of the first band-adjusted signal and output a first peak voltage in accordance with the detected peak voltage.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 17, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi UEMURA, Keiji TANAKA
  • Publication number: 20230194905
    Abstract: According to one embodiment, an optical module includes: a lid having a first face and a second face, the lid including a bump, a wiring, and a through via; an optical circuit element; a first integrated circuit (IC); a first block bonded to the first IC by a first adhesive; a temperature control element bonded to the optical circuit element; and a housing having an opening and a third face provided inside the opening, the housing being configured to house the first IC, the optical circuit element, the first block, and the temperature control element, the third face being bonded to the first block and the temperature control element by a second adhesive, the housing being hermetically sealed with the lid.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 22, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji TANAKA, Hiroshi Uemura, Taichi Misawa
  • Publication number: 20230194903
    Abstract: An optical module includes: a housing having a first face and a second face parallel to the first face; a first block fixed to the first face of the housing by a first adhesive; an integrated circuit (IC) fixed to the first block by a second adhesive having a thickness larger than a thickness of the first adhesive; a thermoelectric cooler (TEC) fixed to the second face of the housing; an optical circuit element fixed to the TEC; and an interconnection board mounted on the IC and the optical circuit element, the interconnection board being configured to electrically couple the IC to the optical circuit element. The first block is sandwiched between the housing and the IC. The TEC is sandwiched between the housing and the optical circuit element.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 22, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi UEMURA, Keiji Tanaka, Taichi Misawa
  • Publication number: 20230092750
    Abstract: A reception circuit includes an input terminal configured to receive an input current; a voltage signal circuit being configured to convert a current signal into a voltage signal; a reference voltage circuit configured to generate a reference voltage in accordance with a first feedback current; a differential amplifier circuit configured to generate a differential signal in accordance with a voltage difference between the voltage signal and the reference voltage; and an offset control circuit configured to generate the first feedback current and a second feedback current, adjust the first feedback current when the voltage signal has an average voltage value greater than the reference voltage, and subtract the second feedback current from the input current such that the offset of the differential signal falls within the tolerance when the voltage signal has an average voltage value smaller than the reference voltage.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 23, 2023
    Inventors: Yoshiyuki SUGIMOTO, Keiji TANAKA
  • Patent number: 11601203
    Abstract: A transimpedance amplifier includes a feedback circuit that generates a bypass current in accordance with a charging voltage of a capacitor based on a difference between a voltage signal and a reference voltage signal, a differential amplifier circuit that generates a differential signal in accordance with the difference between the voltage signal and the reference voltage signal, and a detector circuit that resets the charging voltage of the capacitor in response to a detection of end of a burst optical signal. The feedback circuit detects start of the burst optical signal based on the charging voltage, maintains a time constant at a first time constant for a predetermined period from the detection of the start of the burst optical signal, and, upon an elapse of the predetermined period, switches the time constant from the first time constant to a second time constant larger than the first time constant.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 7, 2023
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Tanaka
  • Patent number: 11595010
    Abstract: An optical receiver disclosed includes a bias terminal, an input terminal, a photodiode, an amplifier circuit, a first resistor, a bypass circuit, a filter circuit, and a control circuit. The photodiode receives a bias from the filter circuit through the bias terminal, and outputs a current signal to the amplifier circuit through the input terminal. The amplifier circuit converts an input current to an output voltage. The bypass circuit electrically connected to the input terminal decreases a first input impedance viewed from the input terminal, when activated, and increases the first input impedance, when deactivated. The filter circuit increases a second input impedance viewed from the bias terminal, when a dumping function thereof is activated, and decreases the second input impedance, when the dumping function is deactivated. The control circuit activates the dumping function and the bypass circuit, when the output voltage is larger than a certain voltage.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: February 28, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoki Itabashi, Keiji Tanaka
  • Patent number: 11588476
    Abstract: An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: February 21, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi Uemura, Keiji Tanaka
  • Publication number: 20230049828
    Abstract: Provided is a lubricating grease used for lubricating mechanical elements having a reciprocating sliding ball interposed therebetween and maintaining flaking resistance even under a high load in mechanical elements having a reciprocating sliding ball interposed therebetween. The present invention therefore provides a grease composition comprising a base oil (a), a diurea compound (b), an amide compound (c), and a thiophosphorous compound or a thiophosphoric acid ester compound (d), wherein the diurea compound (b) includes a compound represented by Formula (1) R1—NHCONH—R2—NHCONH—R3 (1) wherein R1 and R3 represent an acyclic aliphatic hydrocarbon group having from 8 to 20 carbon atoms, and R2 represents a diphenylmethane group.
    Type: Application
    Filed: January 14, 2021
    Publication date: February 16, 2023
    Inventors: Hiroki YANO, Keiji TANAKA
  • Publication number: 20230011340
    Abstract: A receiver circuit includes an input terminal for receiving an input current signal, a transimpedance amplifier having an input node, the transimpedance amplifier converting a current signal input to the input node into a voltage signal, an inductor having a first terminal and a second terminal, and a bypass circuit. The first terminal is coupled to the input terminal and the second terminal is coupled to the input node. The bypass circuit includes a bias circuit supplying a bias voltage, a first variable resistor coupled between the first terminal and the bias circuit, a second variable resistor coupled between the second terminal and the bias circuit, and an impedance adjustment circuit including a resistor and a capacitor connected in parallel to the resistor, the impedance adjustment circuit connected in series to at least one of the first variable resistor and the second variable resistor.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 12, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji KUMAGAI, Yoshiyuki SUGIMOTO, Keiji TANAKA
  • Publication number: 20230002650
    Abstract: The present invention is to provide an adhesive composition which comprises a copolymer A which contains a recurring unit having a cyclic ether structure and a recurring unit having a benzophenone structure, and a copolymer B which contains a recurring unit having a betaine structure and a recurring unit having a hydroxyl group, a cured product thereof, and a method for producing the cured product. The adhesive composition of the present invention is capable of curing in water, has high hydrophilicity, and is capable of forming a cured product having an excellent ability to inhibit adhesion of biological substances.
    Type: Application
    Filed: August 25, 2020
    Publication date: January 5, 2023
    Applicants: KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION, NISSAN CHEMICAL CORPORATION
    Inventors: Masayasu TOTANI, Keiji TANAKA, Hisao MATSUNO, Masaaki OZAWA, Junko KATAYAMA
  • Patent number: 11486760
    Abstract: A receiving circuit includes a first input terminal and a second input terminal, an input circuit that includes a first node, a second node, a first inductor, a second inductor, a first variable resistive element, and a second variable resistive element. The first variable resistive element is electrically connected between the first node and the second input terminal, and the second variable resistive element is electrically connected between the second node and the first input terminal. The receiving circuit further includes a differential amplifier configured to generate a differential voltage signal in accordance with a differential current signal. The receiving circuit still further includes a control circuit configured to perform detection of an amplitude of the differential voltage signal and change a resistance value of the first variable resistive element and a resistance value of the second variable resistive element based on a result of the detection.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: November 1, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Kumagai, Yoshiyuki Sugimoto, Keiji Tanaka
  • Publication number: 20220295630
    Abstract: A printed board includes a first wiring layer including a first terminal, a second wiring layer including a second terminal facing to the first terminal, a dielectric layer interposed between the first wiring layer and the second wiring layer and having an end face, and a plurality of through-hole vias configured to electrically connect the first terminal and the second terminal. The plurality of through-hole vias includes a first through-hole via which is closest to an end-face edge of the first terminal, and a second through-hole via which is closest to an inner edge of the second terminal. The end-face edge being closer to the end face than the inner edge. A distance between the first through-hole via and the end-face edge is equal to or smaller than one eighth of a signal wavelength of a high speed signal transmitted through the first terminal.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 15, 2022
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Taichi MISAWA, Keiji TANAKA
  • Patent number: 11437962
    Abstract: A differential amplifier circuit includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generate a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series between the drain and the source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between the gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 6, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoki Itabashi, Keiji Tanaka