Patents by Inventor Keiji Tanaka

Keiji Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11486760
    Abstract: A receiving circuit includes a first input terminal and a second input terminal, an input circuit that includes a first node, a second node, a first inductor, a second inductor, a first variable resistive element, and a second variable resistive element. The first variable resistive element is electrically connected between the first node and the second input terminal, and the second variable resistive element is electrically connected between the second node and the first input terminal. The receiving circuit further includes a differential amplifier configured to generate a differential voltage signal in accordance with a differential current signal. The receiving circuit still further includes a control circuit configured to perform detection of an amplitude of the differential voltage signal and change a resistance value of the first variable resistive element and a resistance value of the second variable resistive element based on a result of the detection.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: November 1, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Kumagai, Yoshiyuki Sugimoto, Keiji Tanaka
  • Publication number: 20220295630
    Abstract: A printed board includes a first wiring layer including a first terminal, a second wiring layer including a second terminal facing to the first terminal, a dielectric layer interposed between the first wiring layer and the second wiring layer and having an end face, and a plurality of through-hole vias configured to electrically connect the first terminal and the second terminal. The plurality of through-hole vias includes a first through-hole via which is closest to an end-face edge of the first terminal, and a second through-hole via which is closest to an inner edge of the second terminal. The end-face edge being closer to the end face than the inner edge. A distance between the first through-hole via and the end-face edge is equal to or smaller than one eighth of a signal wavelength of a high speed signal transmitted through the first terminal.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 15, 2022
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Taichi MISAWA, Keiji TANAKA
  • Patent number: 11437962
    Abstract: A differential amplifier circuit includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generate a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series between the drain and the source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between the gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 6, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoki Itabashi, Keiji Tanaka
  • Patent number: 11411542
    Abstract: A transimpedance amplifier circuit includes a single-input amplifier that converts a current signal into a voltage signal, a control current circuit that generates a control current based on the voltage signal and a reference voltage signal, and a bypass circuit. The bypass circuit includes a control circuit configured to receive the control current, a feedback current source configured to generate a direct current (DC) bypass current, and a variable resistance circuit configured to generate an alternating current (AC) bypass current. The control circuit includes a first current mirror circuit that varies the DC bypass current via the feedback current source in accordance with the control current, and a second current mirror circuit that varies the AC bypass current via the variable resistance circuit in accordance with the control current and an offset current.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 9, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Keiji Tanaka
  • Patent number: 11398866
    Abstract: An optical semiconductor device includes an insulative base having first and second surfaces, and a metallic pattern formed on the first surface and including a grounding pattern, a transmission pattern having a line connected between input and output ends thereof, and first and second patterns, where the first pattern is located between the second surface crossing a direction parallel to the first surface, and the second pattern. The device includes a laser chip, mounted on the first surface between the transmission pattern and the first and second patterns, and having an electrode and a light emitting end located between the electrode and the second surface, a first wire connecting the output end to the electrode, a second wire connecting the electrode to the first pattern, an inductor provided on the first surface connected between the first and second patterns and formed by a meander wiring or a bonding wire.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: July 26, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Taichi Misawa, Keiji Tanaka
  • Patent number: 11394352
    Abstract: A transimpedance amplifier circuit for generating an output voltage in accordance with an input current includes an offset resistor, a common emitter inverting amplifier having a first input and a first output, the first input receiving the input current, an emitter follower having a second input and a second output, the second input being coupled to the first output through the offset resistor, the second output outputting the output voltage, a feedback resistor connected between the second output and the first input, a variable current source connected to a node between the offset resistor and the second input, the variable current source configured to provide an offset current to the offset resistor, the offset current having a current value varied in accordance with a control signal, and a control circuit configured to generate the control signal so that an average voltage of the first output approaches a preset voltage value.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: July 19, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshiyuki Sugimoto, Keiji Tanaka, Seiji Kumagai
  • Patent number: 11362629
    Abstract: A transimpedance amplifier (TIA) circuit disclosed includes an input terminal, a first TIA circuit, a second TIA circuit, a field effect transistor (FET), and a gain control circuit. The first TIA circuit outputs a voltage signal from a first output in accordance with an input current received at a first input electrically connected to the input terminal. The second TIA circuit outputs a reference signal from a second output. The FET varies a resistance between a first current terminal and a second current terminal in accordance with a control signal applied to a control terminal. The first current terminal is electrically connected to the input terminal. The second current terminal is electrically connected to the second output of the second TIA circuit. The gain control circuit detects an amplitude of the voltage signal and generates the control signal according to a detection result of the amplitude.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: June 14, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoki Itabashi, Keiji Tanaka
  • Patent number: 11349444
    Abstract: In a transimpedance amplifier circuit, a control current circuit generates a control current based on a voltage signal and a reference voltage signal and includes an integrating circuit that generates a differential integral signal based on the voltage signal and the reference voltage signal, and a transconductance amplifying circuit that includes a first transconductance circuit that generates a first output current in accordance with the differential integral signal, a second transconductance circuit that generates a second output current in accordance with the differential integral signal, and a current source that supplies a third output current, and a control circuit has an input electrically connected to an output of the first transconductance circuit, an output of the second transconductance circuit, and an output of the current source.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 31, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Keiji Tanaka
  • Publication number: 20220158448
    Abstract: An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a first node, a second diode circuit connected between the second output terminal and the first node, a first intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at a second node different from the first node, a first intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, a detection circuit configured to generate a trigger signal in accordance with the first intermediate voltage, and a switch circuit configured to electrically connect the first node to a ground line in accordance with the trigger signal.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 19, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi UEMURA, Keiji TANAKA
  • Publication number: 20220158447
    Abstract: An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a common node, a second diode circuit connected between the second output terminal and the common node, an intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at the common node, an intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, and a clamp circuit configured to electrically connect the common node to a ground line in accordance with the intermediate voltage.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 19, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi UEMURA, Keiji TANAKA
  • Publication number: 20220157217
    Abstract: A driving circuit includes first and second input signal terminals, first and second output signal terminals, constant current sources, first and second transistors having control terminals connected to the first and second input signal terminals, third and fourth transistors each having a control terminal to which a first bias voltage is applied, first and second inductors each having a first inductance, and third and fourth inductors each having a second inductance larger than the first inductance. The driving circuit further includes fifth and sixth transistors each having a control terminal to which a second bias voltage is applied, outflow terminals connected to inflow terminals of the third and fourth transistors via the first and second inductors, and inflow terminals connected to the first and second output signal terminals via the third and fourth inductors.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 19, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi UEMURA, Keiji TANAKA
  • Publication number: 20220149790
    Abstract: A variable gain amplifier circuit includes first and second input terminals, first and second output terminals, first and second transistors respectively having bases electrically connected to the first and second input terminals and having collectors electrically connected to the first and second output terminals, and a degeneration circuit connected between emitters of the first and second transistors. The degeneration circuit has first and second MOS transistors each having two current terminals connected in series between the emitters of the first and second transistors, series resistor circuits, first and second current sources, two resistive elements connected between the first and second current sources and gates of the first and second MOS transistors, and two resistive elements connected between the first and second current sources and two nodes of the series resistor circuits.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi UEMURA, Keiji TANAKA
  • Publication number: 20220149826
    Abstract: An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi UEMURA, Keiji TANAKA
  • Publication number: 20220109507
    Abstract: A transimpedance amplifier includes a feedback circuit that generates a bypass current in accordance with a charging voltage of a capacitor based on a difference between a voltage signal and a reference voltage signal, a differential amplifier circuit that generates a differential signal in accordance with the difference between the voltage signal and the reference voltage signal, and a detector circuit that resets the charging voltage of the capacitor in response to a detection of end of a burst optical signal. The feedback circuit detects start of the burst optical signal based on the charging voltage, maintains a time constant at a first time constant for a predetermined period from the detection of the start of the burst optical signal, and, upon an elapse of the predetermined period, switches the time constant from the first time constant to a second time constant larger than the first time constant.
    Type: Application
    Filed: September 28, 2021
    Publication date: April 7, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Keiji TANAKA
  • Publication number: 20220057262
    Abstract: A receiving circuit includes a first input terminal and a second input terminal, an input circuit that includes a first node, a second node, a first inductor, a second inductor, a first variable resistive element, and a second variable resistive element. The first variable resistive element is electrically connected between the first node and the second input terminal, and the second variable resistive element is electrically connected between the second node and the first input terminal. The receiving circuit further includes a differential amplifier configured to generate a differential voltage signal in accordance with a differential current signal. The receiving circuit still further includes a control circuit configured to perform detection of an amplitude of the differential voltage signal and change a resistance value of the first variable resistive element and a resistance value of the second variable resistive element based on a result of the detection.
    Type: Application
    Filed: August 18, 2021
    Publication date: February 24, 2022
    Inventors: Seiji KUMAGAI, Yoshiyuki SUGIMOTO, Keiji TANAKA
  • Patent number: 11228293
    Abstract: A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 18, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshiyuki Sugimoto, Keiji Tanaka
  • Patent number: 11220650
    Abstract: A grease composition containing a base oil and a calcium complex soap as a thickening agent, wherein a C18-22 straight chain, substituted or unsubstituted higher fatty acid; a substituted or unsubstituted aromatic monocarboxylic acid having a benzene ring; a C2-4 straight-chain saturated lower fatty acid; and a substituted or unsubstituted saturated dicarboxylic acid are used as carboxylic acids constituting the calcium complex soap.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 11, 2022
    Assignee: SHELL OIL COMPANY
    Inventors: Kazuya Watanabe, Keiji Tanaka, Hiroki Yano
  • Patent number: 11198830
    Abstract: The invention provides a grease composition, being a grease composition containing a base oil and, as a thickener a calcium complex soap, and being a grease composition using for the carboxylic acids forming the aforementioned calcium complex soap substituted or unsubstituted C18-22 straight-chain higher fatty acids, aromatic monocarboxylic aromatic acids having substituted or unsubstituted benzene rings and C2-4 straight-chain saturated lower fatty acids, wherein the aforementioned substituted or unsubstituted C18-22 straight-chain higher fatty acids include behenic acid and the amount of behenic acid used, as a mass ratio in terms of the total amount of the aforementioned substituted or unsubstituted C18-22 straight-chain higher fatty acids used, is from 25 mass % up to 70 mass %.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 14, 2021
    Assignee: SHELL OIL COMPANY
    Inventors: Keiji Tanaka, Kazuya Watanabe
  • Patent number: 11199840
    Abstract: A mover control system according to an embodiment includes a controller, a node generator, and a path generator. The controller controls a mover traveling within a predetermined area. The node generator generates a pair of specified nodes at respective arbitrary locations on a map corresponding to the predetermined area. The pair of specified nodes are nodes where the mover is controllable. The path generator generates a path between the pair of specified nodes. The controller makes the mover travel along a traveling route corresponding to the path within the predetermined area.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: December 14, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideo Morita, Takashi Ooyama, Koji Arimura, Keiji Tanaka, Yutaka Mori
  • Publication number: 20210359761
    Abstract: An optical semiconductor device includes an insulative base having first and second surfaces, and a metallic pattern formed on the first surface and including a grounding pattern, a transmission pattern having a line connected between input and output ends thereof, and first and second patterns, where the first pattern is located between the second surface crossing a direction parallel to the first surface, and the second pattern. The device includes a laser chip, mounted on the first surface between the transmission pattern and the first and second patterns, and having an electrode and a light emitting end located between the electrode and the second surface, a first wire connecting the output end to the electrode, a second wire connecting the electrode to the first pattern, an inductor provided on the first surface connected between the first and second patterns and formed by a meander wiring or a bonding wire.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 18, 2021
    Inventors: Taichi MISAWA, Keiji TANAKA