Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Abstract: According to one embodiment, it is provided that an image compressor includes an image data controller, first to third encoders and an encoded data generator. The image data controller extracts first to third pixels. The first encoder encodes a target first pixel and generates a first encoded pixel. The second encoder encodes a target second pixel and generates a second encoded pixel. The third encoder encodes a target third pixel and generates a third encoded pixel. The encoded data generator combines the first to third encoded pixels and generates encoded data.

Abstract: According to one embodiment, an image encode controller includes a chroma component adjuster, a difference generator, a quantizer, an inverse-quantizer, and a variable codeword length encoder. The chroma component adjuster adjusts an original color component in accordance with a quantization coefficient to generate an adjusted chroma component. The difference generator generates a difference pixel component. The quantizer quantizes an output of the difference generator based on the quantization coefficient. The inverse-quantizer inversely quantizes an output of the quantizer based on the quantization coefficient. The variable codeword length encoder performs variable codeword length encoding with respect to an output of the quantizer to generate encoded data.

Abstract: According to one embodiment, an image processing system includes a pickup apparatus, a motion vector generator, a motion vector converter, a motion vector interpolator, a correction amount generator, and a correcting module. The pickup apparatus is configured to capture an image per scanning line and to generate an input video signal from the captured image. The motion vector generator is configured to generate a first horizontal direction motion vector and a first vertical direction motion vector indicative of a horizontal direction moving distance and a vertical direction moving distance respectively between frames in the input video signal.

Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

Abstract: An image coding apparatus includes a particular region detecting unit configured to detect from an input picture a particular region including a particular picture, the particular region detected as a region within the input picture which has a hue within a predetermined range corresponding to an average hue of the particular picture and which has an amount of movement between different frames which is equal to or larger than a threshold. A coding unit generates a coded stream by performing coding processing that is intra-frame coding or interframe coding on the input picture, and performs with respect to the particular region a processing of embedding initial conditions into the coded stream, instead of performing the interframe coding.

Abstract: According to one embodiment, an image processing device includes a motion vector generator, a correction amount generator, and a correcting module. The motion vector generator is configured to generate a horizontal direction motion vector and a vertical direction motion vector of an input video signal photographed in an order of scanning lines. The correction amount generator is configured to generate a horizontal direction correction amount based on the horizontal direction motion vector and the vertical direction motion vector by each scanning line, and generate a vertical direction correction amount based on the vertical direction motion vector by a scanning line. The correcting module is configured to correct the input video signal to generate an output video signal based on the horizontal direction correction amount and the vertical direction correction amount.

Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Abstract: A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.

Abstract: A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.

Abstract: An input unit that sequentially writes a digital image signal to be input in a first buffer while counting number of pixels of the digital image signal, and that writes the written digital image signal in a second buffer; and a command fetching/issuing unit that calculates a position of a pixel based on process delay information that is added to an image processing command and that indicates a delay amount required until image processing by the command is started since the input of the digital image signal, and a counter value indicating the number of pixels, and that issues the image processing command when the position of the pixel is in a valid area are included. Image processing is performed on pixels written in the second buffer based on the issued image processing command.

Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

Abstract: A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address.

Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Abstract: An image coding apparatus includes a particular region detecting unit configured to detect a particular region whose hue is within a predetermined range and whose amount of movement or amount of shift between different frames is a threshold or more from chronologically input pictures forming an image; and a coding unit configured to perform coding on a picture in a frame in which the particular region detected by the particular region detecting unit is replaced with a predetermined picture other than the particular region, while detecting a motion vector between the frames.