Abstract: A semiconductor device includes a main semiconductor region and a current detecting region. The main semiconductor region and the current detecting region have a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type, first semiconductor regions of a second conductivity type, second semiconductor regions of the first conductivity type, trenches, first high-concentration regions of the second conductivity type, and second high-concentration regions of the second conductivity type. An active region through which a current flows when the current detecting region is in an on-state has a first cell region that operates as a transistor and second cell regions that are provided, respectively, in four corners of the first cell region and operate only as diodes and not as a transistor.

Abstract: A source pad of a main semiconductor element is electrically connected to an n+-type source region via a barrier metal. A temperature sensing part is a poly-silicon diode formed by a pn junction between a p-type poly-silicon layer that is a p-type anode region and an n-type poly-silicon layer that is an n-type cathode region. The temperature sensing part is provided, via the field insulating film, on a front surface of a same semiconductor substrate as the main semiconductor element. An anode pad and a cathode pad are in direct contact with the p-type poly-silicon layer and the n-type poly-silicon layer, respectively. The source pad, the anode pad, and the cathode pad are aluminum alloy films.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type1, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate insulating films, gate electrodes, a first electrode, and a second electrode. The second semiconductor layer has a second semiconductor region of a second conductivity type, an impurity concentration of the second semiconductor region increases in the depth direction, has a maximum value at a predetermined depth, and from the predetermined depth, in the depth direction, decreases; a half-width of the impurity concentration is 0.15 ?m or less; and an impurity concentration of the plurality of first semiconductor regions is constant in the depth direction.

Abstract: In an intermediate region surrounding a periphery of an active region, a gate polysilicon wiring layer is provided on a gate insulating film at a front surface of a semiconductor substrate, via a field oxide film. An inner end portion of the gate polysilicon wiring layer faces a p-type region of a surface region at the front surface of the semiconductor substrate, via only the gate insulating film. In the intermediate region, at corners thereof facing corners of the active region, a low carrier lifetime region containing a carrier lifetime killer is provided so as to overlap the p-regions and, in a depth direction, face the gate polysilicon wiring layer, whereby the lifetime of the minority carriers of the corner portions of the intermediate region is shorter than the lifetime of the minority carriers of linear portions of the intermediate region.

Abstract: A silicon carbide semiconductor device includes an n-type drift layer disposed on an n-type silicon carbide substrate; an n-type current spreading layer disposed on a top surface of the drift layer, having a higher impurity concentration than the drift layer; a p-type base region disposed on a top surface of the current spreading layer; a p-type gate-bottom protection region located in the current spreading layer; a p-type base-bottom embedded region located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; an insulated-gate electrode structure disposed in a trench penetrating the base region to reach the gate-bottom protection region, and a lower recombination region disposed in a lower portion of the drift layer, including crystal defects configured to recombine minority carriers injected into the drift layer.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; and a gate electrode having a striped-shape and provided on a gate insulating film. The silicon carbide semiconductor device further includes a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; a step film provided on the first electrode; a plating film provided on the first electrode and the step film; and a solder on the plating film. The step film is provided on the first electrode on which the solder and the plating film are provided, the step film being provided so as to be embedded in grooves formed on the first electrode.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a first semiconductor region of the first conductivity type. The semiconductor device further includes a gate electrode provided in a plurality of trenches via gate insulating films, a protruding portion disposed on the second semiconductor layer at a bridge area between two adjacent ones of the trenches in a direction orthogonal to the trenches, an interlayer insulating film provided on the gate electrode, and having contact holes that form a striped pattern, a first electrode on the interlayer insulating film and in the contact holes, a plating film provided in a plating area, and a solder on the plating film.

Abstract: In an effective region of an active region, a main semiconductor element and a source pad thereof are disposed. A non-operating region of the active region excludes the effective region and is a high-function region in which a gate pad of the main semiconductor element and other electrode pads are disposed. An edge termination region and the electrode pads are separated by an interval equivalent to at least a width of one unit cell of the main semiconductor element. In the high-function region, at a border of the edge termination region, a lead-out electrode is provided on a front surface of a semiconductor substrate. The lead-out electrode has a function of leading out displacement current that flows to the high-function region from the edge termination region when the main semiconductor element is OFF. Thus, destruction at the edge termination region may be suppressed.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate electrode, a first electrode, and a gate electrode pad. A first lower region opposing the gate electrode pad in a depth direction has a carrier recombination rate that is lower than that of a second lower region opposing the first electrode in the depth direction. With such a configuration, when high electric potential is applied to a source electrode and a built-in PN diode is driven, the generation of crystal defects may be suppressed.

Abstract: A silicon carbide semiconductor device has a rectangle-shaped active region in which a main current flows, and a termination region surrounding the active region in a plan view. The device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type on the front surface of the substrate, a second semiconductor layer of a second conductivity type, at a surface at the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer, the second semiconductor region disposed from a periphery of the active region to reach the termination region, and extending along each of directions of four sides of the active region. At the four sides of the active region, a cross-sectional structure of each layer and each region of the device is identical to one another.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed.

Abstract: In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n+ starting substrate, an n? drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.

Abstract: A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type; an active region in which a main current flows provided on the semiconductor substrate; a termination region disposed outside of the active region and in which a voltage withstanding structure is formed; and a damaged region disposed outside the termination region and in which crystallinity is impaired, the damaged region being exposed at a cut surface that is formed when singulation is performed.

Abstract: An interlayer insulating film covers a gate electrode and a gate insulating film embedded in a trench. A source electrode includes a first TiN film, a NiSi film, a Ti film, a second TiN film, and an Al alloy film. The first TiN film covers a part of the interlayer insulating film so as to not contact a semiconductor substrate at a bottom of a contact hole. The NiSi film forms an ohmic contact with the semiconductor substrate in the contact hole. The Ti film, the second TiN film, and the Al alloy film are sequentially stacked on surfaces of the first TiN film and the NiSi film, spanning a front surface of the semiconductor substrate, from on the interlayer insulating film. A terminal pin is soldered to the source electrode 16, in an upright position orthogonal to the front surface of the semiconductor substrate.

Abstract: In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n+ starting substrate, an n? drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.

Abstract: A silicon carbide semiconductor device has a rectangle-shaped active region in which a main current flows, and a termination region surrounding the active region in a plan view. The device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type on the front surface of the substrate, a second semiconductor layer of a second conductivity type, at a surface at the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer, the second semiconductor region disposed from a periphery of the active region to reach the termination region, and extending along each of directions of four sides of the active region. At the four sides of the active region, a cross-sectional structure of each layer and each region of the device is identical to one another.

Abstract: In an effective region of an active region, a main semiconductor element and a source pad thereof are disposed. A non-operating region of the active region excludes the effective region and is a high-function region in which a gate pad of the main semiconductor element and other electrode pads are disposed. An edge termination region and the electrode pads are separated by an interval equivalent to at least a width of one unit cell of the main semiconductor element. In the high-function region, at a border of the edge termination region, a lead-out electrode is provided on a front surface of a semiconductor substrate. The lead-out electrode has a function of leading out displacement current that flows to the high-function region from the edge termination region when the main semiconductor element is OFF. Thus, destruction at the edge termination region may be suppressed.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a first semiconductor region of the first conductivity type. The semiconductor device further includes a gate electrode provided in a plurality of trenches via gate insulating films, a protruding portion disposed on the second semiconductor layer at a bridge area between two adjacent ones of the trenches in a direction orthogonal to the trenches, an interlayer insulating film provided on the gate electrode, and having contact holes that form a striped pattern, a first electrode on the interlayer insulating film and in the contact holes, a plating film provided in a plating area, and a solder on the plating film.

Abstract: A source pad of a main semiconductor element is electrically connected to an n+-type source region via a barrier metal. A temperature sensing part is a poly-silicon diode formed by a pn junction between a p-type poly-silicon layer that is a p-type anode region and an n-type poly-silicon layer that is an n-type cathode region. The temperature sensing part is provided, via the field insulating film, on a front surface of a same semiconductor substrate as the main semiconductor element. An anode pad and a cathode pad are in direct contact with the p-type poly-silicon layer and the n-type poly-silicon layer, respectively. The source pad, the anode pad, and the cathode pad are aluminum alloy films.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.