Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate electrode, a first electrode, and a gate electrode pad. A first lower region opposing the gate electrode pad in a depth direction has a carrier recombination rate that is lower than that of a second lower region opposing the first electrode in the depth direction. With such a configuration, when high electric potential is applied to a source electrode and a built-in PN diode is driven, the generation of crystal defects may be suppressed.

Abstract: An interlayer insulating film covers a gate electrode and a gate insulating film embedded in a trench. A source electrode includes a first TiN film, a NiSi film, a Ti film, a second TiN film, and an Al alloy film. The first TiN film covers a part of the interlayer insulating film so as to not contact a semiconductor substrate at a bottom of a contact hole. The NiSi film forms an ohmic contact with the semiconductor substrate in the contact hole. The Ti film, the second TiN film, and the Al alloy film are sequentially stacked on surfaces of the first TiN film and the NiSi film, spanning a front surface of the semiconductor substrate, from on the interlayer insulating film. A terminal pin is soldered to the source electrode 16, in an upright position orthogonal to the front surface of the semiconductor substrate.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; and a gate electrode having a striped-shape and provided on a gate insulating film. The silicon carbide semiconductor device further includes a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; a step film provided on the first electrode; a plating film provided on the first electrode and the step film; and a solder on the plating film. The step film is provided on the first electrode on which the solder and the plating film are provided, the step film being provided so as to be embedded in grooves formed on the first electrode.

Abstract: A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type; an active region in which a main current flows provided on the semiconductor substrate; a termination region disposed outside of the active region and in which a voltage withstanding structure is formed; and a damaged region disposed outside the termination region and in which crystallinity is impaired, the damaged region being exposed at a cut surface that is formed when singulation is performed.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.

Abstract: To prevent a malfunction of an overcurrent protection circuit without increasing an on-voltage, and to suppress a short circuit capacity, thus further reducing a switching loss, a trench gate IGBT is provided in which is incorporated a sense IGBT connected in parallel to a main IGBT, where only the sense IGBT portion includes a p-type channel region all over in a semiconductor substrate between adjacent parallel striped trenches, so that the capacitance of the MOS gate of the sense IGBT is smaller than the capacitance of the MOS gate of the main IGBT.

Abstract: To prevent a malfunction of an overcurrent protection circuit without increasing an on-voltage, and to suppress a short circuit capacity, thus further reducing a switching loss, a trench gate IGBT is provided in which is incorporated a sense IGBT connected in parallel to a main IGBT, where only the sense IGBT portion includes a p-type channel region all over in a semiconductor substrate between adjacent parallel striped trenches, so that the capacitance of the MOS gate of the sense IGBT is smaller than the capacitance of the MOS gate of the main IGBT.