Patents by Inventor Keisuke Ueda

Keisuke Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9822450
    Abstract: The present invention provides a vacuum processing apparatus capable of reducing attachment of particles generated in a processing space to an inner wall of a chamber, and of easily adjusting pressure in the processing space while introducing a gas into the processing space at a desired flow rate. A vacuum processing apparatus according to one embodiment includes: a container; a gas exhaust portion; a substrate holder configured to retain a substrate; a shield provided to surround the substrate holder and dividing an inside of the container into a processing space and an outside space; a gas introducing portion; a plasma generating portion; and an exhaust portion provided to the shield having a communication path through which the processing space and the outside space communicate, wherein at least part of the communication path is hidden from a region where the plasma generating portion generates the plasma.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: November 21, 2017
    Assignee: Canon Anelva Corporation
    Inventors: Toshikazu Nakazawa, Norihito Tsukamoto, Keisuke Ueda, Eiji Ozaki
  • Patent number: 9817768
    Abstract: Provided is a storage system including: a storage medium including a plurality of physical storage areas having an upper limit number of rewrites, and a medium controller that controls I/O (input/output) of data to/from the plurality of physical storage areas; and a storage controller connected to the storage medium, wherein when any of the physical storage areas is not allocated to a write destination logical storage area among a plurality of logical storage areas, the medium controller allocates a vacant physical storage area among the plurality of physical storage areas to the write destination logical storage area and writes write target data to the allocated vacant physical storage area, and the plurality of logical storage areas includes an available logical area group determined based on a relationship between an available capacity of a logical storage capacity and a rewrite frequency of the plurality of physical storage areas.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: November 14, 2017
    Assignee: HITACHI, LTD.
    Inventors: Keisuke Ueda, Go Uehara, Kenta Ninose, Hiroshi Hirayama
  • Patent number: 9743471
    Abstract: A lighting device which outputs a DC current to a load, the lighting device including: a downconverter circuit which includes a switching element and steps down a DC voltage input to the downconverter circuit; and a controller which controls turning on and off of the switching element, wherein the controller has operating modes including a detection mode in which the controller detects a time taken for a current through the switching element to reach a predetermined value after the switching element turns on, the current through the switching element representing the DC current output to the load.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: August 22, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Katsuyoshi Nakada, Keisuke Ueda, Kenichi Fukuda
  • Publication number: 20160374162
    Abstract: A lighting device which outputs a DC current to a load, the lighting device including: a downconverter circuit which includes a switching element and steps down a DC voltage input to the downconverter circuit; and a controller which controls turning on and off of the switching element, wherein the controller has operating modes including a detection mode in which the controller detects a time taken for a current through the switching element to reach a predetermined value after the switching element turns on, the current through the switching element representing the DC current output to the load.
    Type: Application
    Filed: June 10, 2016
    Publication date: December 22, 2016
    Inventors: Katsuyoshi NAKADA, Keisuke UEDA, Kenichi FUKUDA
  • Patent number: 9368331
    Abstract: The present invention provides a highly efficient magnetron sputtering apparatus in which a ground shield made of a magnetic material is disposed on the outer circumference of a target, the sputtering apparatus being capable of reducing unintended discharge between a cathode and the ground shield. The sputtering apparatus according to an embodiment includes: a backing plate connected to a power supply and having a target mounting surface; a magnet disposed on the back surface of the backing plate; a grounded shield containing a magnetic material and surrounding the target mounting surface; and a fixation part located between the shield and the backing plate at an outer circumference of the target mounting surface and serving as a magnetic member. This structure reduces magnetic field lines which pass through a space between the shield and the fixation part.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 14, 2016
    Assignee: Canon Anelva Corporation
    Inventors: Masato Shinada, Keisuke Ueda
  • Patent number: 9345100
    Abstract: A no-load detection circuit includes an inductance device, an impedance device and a switch circuit. The inductance device is interposed between a choke coil and a first output terminal, which is at a high potential side, so as to be magnetically coupled to the choke coil. The impedance device is connected in series with the inductance device between the inductance device and the first output terminal. The switch circuit is configured to be turned on when a value of electric potential at the first output terminal exceeds a predetermined reference value. The control circuit is configured to stop the switching control if the switch circuit is turned on.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: May 17, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Keisuke Ueda, Nobuo Ukita
  • Patent number: 9294264
    Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: March 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Endo, Keisuke Ueda, Toshiya Uozumi
  • Publication number: 20160019159
    Abstract: Provided is a storage system including: a storage medium including a plurality of physical storage areas having an upper limit number of rewrites, and a medium controller that controls I/O (input/output) of data to/from the plurality of physical storage areas; and a storage controller connected to the storage medium, wherein when any of the physical storage areas is not allocated to a write destination logical storage area among a plurality of logical storage areas, the medium controller allocates a vacant physical storage area among the plurality of physical storage areas to the write destination logical storage area and writes write target data to the allocated vacant physical storage area, and the plurality of logical storage areas includes an available logical area group determined based on a relationship between an available capacity of a logical storage capacity and a rewrite frequency of the plurality of physical storage areas.
    Type: Application
    Filed: October 10, 2013
    Publication date: January 21, 2016
    Applicant: Hitachi, Ltd.
    Inventors: KEISUKE UEDA, Go UEHARA, Kenta NINOSE, Hiroshi HIRAYAMA
  • Publication number: 20150381344
    Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.
    Type: Application
    Filed: September 2, 2015
    Publication date: December 31, 2015
    Inventors: Keisuke UEDA, Toshiya UOZUMI, Ryo ENDO
  • Publication number: 20150303042
    Abstract: The present invention provides a highly efficient magnetron sputtering apparatus in which a ground shield made of a magnetic material is disposed on the outer circumference of a target, the sputtering apparatus being capable of reducing unintended discharge between a cathode and the ground shield. The sputtering apparatus according to an embodiment includes: a backing plate connected to a power supply and having a target mounting surface; a magnet disposed on the back surface of the backing plate; a grounded shield containing a magnetic material and surrounding the target mounting surface; and a fixation part located between the shield and the backing plate at an outer circumference of the target mounting surface and serving as a magnetic member. This structure reduces magnetic field lines which pass through a space between the shield and the fixation part.
    Type: Application
    Filed: June 26, 2015
    Publication date: October 22, 2015
    Inventors: MASATO SHINADA, KEISUKE UEDA
  • Patent number: 9154143
    Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: October 6, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keisuke Ueda, Toshiya Uozumi, Ryo Endo
  • Publication number: 20150282263
    Abstract: A no-load detection circuit includes an inductance device, an impedance device and a switch circuit. The inductance device is interposed between a choke coil and a first output terminal, which is at a high potential side, so as to be magnetically coupled to the choke coil. The impedance device is connected in series with the inductance device between the inductance device and the first output terminal. The switch circuit is configured to be turned on when a value of electric potential at the first output terminal exceeds a predetermined reference value. The control circuit is configured to stop the switching control if the switch circuit is turned on.
    Type: Application
    Filed: February 3, 2015
    Publication date: October 1, 2015
    Inventors: Keisuke UEDA, Nobuo UKITA
  • Patent number: 9127355
    Abstract: Provided is a substrate processing apparatus including an openable and closable lid and being capable of precisely controlling a gap between multiple shields. The substrate processing apparatus includes: an openable and closable lid provided on an opening of a chamber; a first shield provided on a surface of the lid at the chamber side and having an insertion hole; an insertion section fixed to the lid while inserted through the insertion hole, and configured to support the first shield in a manner movable within a predetermined distance; a restriction section provided on an end portion of the insertion section and configured to restrict the movement of the first shield; and biasing means configured to bias the first shield to a member provided inside the chamber when the lid is closed.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 8, 2015
    Assignee: CANON ANELVA CORPORATION
    Inventors: Toshikazu Nakazawa, Norihito Tsukamoto, Keisuke Ueda, Eiji Ozaki
  • Patent number: 9094021
    Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: July 28, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Chihiro Arai, Toshiya Uozumi, Keisuke Ueda
  • Patent number: 9085820
    Abstract: Provided is a substrate processing apparatus including an openable and closable lid and being capable of precisely controlling a gap between multiple shields. The substrate processing apparatus includes: an openable and closable lid provided on an opening of a chamber; a first shield provided on a surface of the lid at the chamber side and having an insertion hole; an insertion section fixed to the lid while inserted through the insertion hole, and configured to support the first shield in a manner movable within a predetermined distance; a restriction section provided on an end portion of the insertion section and configured to restrict the movement of the first shield; and biasing means configured to bias the first shield to a member provided inside the chamber when the lid is closed.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 21, 2015
    Assignee: CANON ANELVA CORPORATION
    Inventors: Toshikazu Nakazawa, Norihito Tsukamoto, Keisuke Ueda, Eiji Ozaki
  • Publication number: 20150078503
    Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 19, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Ryo Endo, Keisuke Ueda, Toshiya Uozumi
  • Patent number: 8963593
    Abstract: A high-frequency signal processing device having a frequency synthesizer (PLL: Phase Locked Loop) is provided. A control circuit measures oscillation frequencies obtained upon setting a bias current of an oscillation circuit to first and second bias setting values and acquires a frequency difference amount of the oscillation frequencies. The frequency difference amount may be acquired as difference amount of setting values of a coarse adjustment capacitance setting signal (CTRM) using, for example, an automatic frequency selector unit. The control circuit retains a relationship of a difference amount of bias setting values and a difference value of setting values of the CTRM and approximating the relationship to a linear function. Thereafter, the control circuit defines, upon switching the bias current during locking of the PLL, the CTRM based on the linear function and switches the CTRM together with the bias current.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Chihiro Arai, Toshiya Uozumi, Keisuke Ueda
  • Publication number: 20150044384
    Abstract: A coating apparatus includes a first water repellent portion that is formed on a liquid supply surface provided in a liquid supply platform to once retain a liquid to be transferred to a coating object, and a hydrophilic portion that is formed around the first water repellent portion. Further, a coating method includes supplying a liquid to a top surface of a liquid supply platform, which is a liquid supply surface formed with a water repellent portion and a hydrophilic portion disposed around the water repellent portion, and transferring by pressing a coating object of the liquid against the liquid that is retained by the liquid supply surface.
    Type: Application
    Filed: July 21, 2014
    Publication date: February 12, 2015
    Inventors: Satoshi Kai, Keisuke Ueda
  • Patent number: 8929502
    Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 6, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Endo, Keisuke Ueda, Toshiya Uozumi
  • Patent number: 8853949
    Abstract: An LED lighting device includes a DC/DC power converter having output terminals coupled to respective lamp sockets. A controller receives signals from a current sensor and a voltage sensor, and controls the DC/DC power converter to increase/decrease an output voltage based on a sensed output current with respect to a target value. A sensed output voltage is compared to predetermined upper and lower limit values, and the DC/DC power converter is disabled when the output voltage exceeds the predetermined upper limit value or falls below the predetermined lower limit. The controller further measures an accumulated lighting time of the device, and after the accumulated lighting time has exceeded a predetermined switching time, decreases the upper limit value monotonously or in increments as the accumulated lighting time passes.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 7, 2014
    Assignee: Panasonic Corporation
    Inventors: Katsunobu Hamamoto, Masafumi Yamamoto, Keisuke Ueda, Hisaya Takikita