Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.

Abstract: In a semiconductor device, a plurality of wiring layers each patterned in a required shape are laminated over both surfaces of an insulating base material with insulating layers interposed therebetween, and electrically connected to one another through via holes piercing the insulating layers in the direction of thickness. A chip is mounted in an embedded manner in one insulating layer over at least one surface of the insulating base material. Electrodes of the chip are connected to one wiring layer. Through holes are formed in portions of the insulating base material, the portions corresponding to a mount area for the chip. Via holes are formed on outwardly extending portions (pad portions) of the wiring layer connected to a conductor layer formed at least on the inner walls of the through holes.

Abstract: A multilayer ceramic coil (4) for use in a compact motor is configured so that ceramic layers (4c) having a plurality of coil patterns (4a) and (4b) printed using a conductive paste are laminated, and that the coil patterns in respective layers are electrically connected via thru-holes (4d) to form a single multilayer ceramic structure having a plurality of phases of patterned-coil.

Abstract: A method for fabricating an electronic component embedded substrate including an electronic component that is embedded within a buildup layer is disclosed. The method includes a first buildup layer lamination step of laminating plural first buildup layers on a core substrate such that the total thickness of the first buildup layers corresponds to the thickness of the electronic component; a cavity formation step of forming a cavity for accommodating the electronic component at the laminated first buildup layers; an accommodating step of accommodating the electronic component within the cavity; and a second buildup layer lamination step of laminating a second buildup layer on the first buildup layers and the electronic component.

Abstract: In a semiconductor device, a plurality of wiring layers each patterned in a required shape are laminated over both surfaces of an insulating base material with insulating layers interposed therebetween, and electrically connected to one another through via holes piercing the insulating layers in the direction of thickness. A chip is mounted in an embedded manner in one insulating layer over at least one surface of the insulating base material. Electrodes of the chip are connected to one wiring layer. Through holes are formed in portions of the insulating base material, the portions corresponding to a mount area for the chip. Via holes are formed on outwardly extending portions (pad portions) of the wiring layer connected to a conductor layer formed at least on the inner walls of the through holes.

Abstract: Disclosed multilayer ceramic coil (4) for use in compact motor is configured that ceramic layers (4c) having a plurality of coil patterns (4a) and (4b) printed using a conductive paste are laminated, and that the coil patterns in respective layers are electrically connected via thru-holes (4d) to form a single multilayer ceramic structure having a plurality of phases of patterned-coil.

Abstract: A semiconductor device substrate comprised of a core substrate on both surfaces or on one surface of which interconnect patterns are formed via resin layers, wherein the core substrate is formed by a material having a heat expansion coefficient close to a semiconductor chip, that is, a heat expansion coefficient closer to a semiconductor chip than the resin layers and the interconnect patterns inside the substrate, a resin layer forming an outermost layer of the substrate is formed using a material having a higher strength and/or a higher elongation than the resin material used for the inner resin layers in the substrate, and thereby cracking, deformation, and other problems arising in the substrate due to the thermal stress occurring between the core substrate and the resin layers in the substrate and interconnect patterns being prevented.

Abstract: A brushless motor includes (a) a rotor magnet having plural magnetic polarities and (b) a stator core facing the rotor magnet via an annular space. The stator core has plural teeth wound by coils, and a teeth width ranges from not less than 1.7 mm to not more than 2.2 mm, or an outer diameter of the rotor core vs. the teeth width ranges from not less than 8 to not more than 12. This structure allows the brushless motor to rotate with less vibrations, lower noise and lower current consumption.