Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.

Abstract: Carbon-doped germanium stressor regions are formed in an nFET device region of a germanium substrate and at a footprint of a functional gate structure. The carbon-doped germanium stressor regions are formed by an epitaxial growth process utilizing monomethylgermane (GeH3—CH3) as the carbon source. The carbon-doped germanium stressor regions that are provided yield more strain in less volume since a carbon atom is much smaller than a silicon atom.

Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Abstract: On-chip, doped semiconductor fuse regions compatible with FinFET CMOS fabrication are formed from the channel regions of selected fins. One or more fin dimensions are optionally reduced in selected channel regions of the fins following dummy gate removal, such as height and/or width. The channel regions from which the fuse regions are formed are doped to provide electrical conductivity, amorphized using ion implantation, and then annealed to form substantially polycrystalline fuse regions. Source/drain regions function as terminals for the fuse regions.

Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.

Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.

Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.

Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.

Abstract: Described herein is a method for manufacturing a stack of semiconductor materials in which a growth substrate is separated from the stack after a semiconductor material, e.g., a Group III nitride semiconductor material, is grown on the substrate. The separation is effected in a spalling procedure in which spalling-facilitating layers are deposited over a protective cap layer that is formed over the Group III-nitride semiconductor material. Such spalling-facilitating layers may include a handle layer, a stressor layer, and an optional adhesion layer. The protective cap layer protects the Group III-nitride from being damaged by the depositing of one or more of the spalling-facilitating layers. After spalling to remove the growth substrate, additional processing steps are taken to provide a semiconductor device that includes undamaged semiconductor material. In one arrangement, the semiconductor material is GaN and includes p-doped GaN region that was undamaged during manufacturing.

Abstract: According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises depositing a transition layer on a substrate, depositing GaN material on the transition layer, forming a contact on the GaN material, depositing a stressor layer on the GaN material, separating the transition layer and the substrate from the GaN material, patterning and removing portions of the GaN material to expose portions of the stressor layer.

Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type layer is formed on or in the p-doped layer. The n-type layer includes ZnO on the p-doped layer to form an electronic device.

Abstract: A method for forming a photovoltaic device includes forming a photovoltaic absorption stack on a substrate including one or more of I-III-VI2 and I2-II-IV-VI4 semiconductor material. A transparent conductive contact layer is deposited on the photovoltaic absorption stack at a temperature less than 200 degrees Celsius. The transparent conductive contact layer has a thickness of about one micron and is formed on a front light-receiving surface. The surface includes pyramidal structures due to an as deposited thickness. The transparent conductive contact layer is wet etched to further roughen the front light-receiving surface to reduce reflectance.

Abstract: A handle substrate having at least one metallization region is provided on a stressor layer that is located above a base substrate such that the at least one metallization region is in contact with a surface of the stressor layer. An upper portion of the base substrate is spalled, i.e., removed, to provide a structure comprising, from bottom to top, a spalled material portion of the base substrate, the stressor layer and the handle substrate containing the at least one metallization region in contact with the surface of the stressor layer.

Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.

Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.

Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

Abstract: According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises depositing a transition layer on a substrate, depositing GaN material on the transition layer, forming a contact on the GaN material, depositing a stressor layer on the GaN material, separating the transition layer and the substrate from the GaN material, patterning and removing portions of the GaN material to expose portions of the stressor layer.

Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.

Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.