Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.

Abstract: A light emitting diode (LED) includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. A p-type confinement layer is provided on the p-type substrate. An emission layer is provided on the p-type confinement layer. An n-type confinement layer is provided on the emission layer. A transparent II-VI n-type contact layer is formed on the n-type confinement layer as a replacement for a current spreading layer, a III-V contact layer and an n-type ohmic contact.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method for reducing substrate bowing resulting from the formation of strained SiGe layers having a high percentage of germanium (“high concentration SiGe”) on silicon substrates. During the epitaxial growth of the high concentration SiGe layer, carbon dopant atoms may be introduced to the crystalline lattice structure of the SiGe, forming a SiGe:C layer. The carbon dopant atoms may reduce tensile strain in the SiGe:C layer during annealing, thereby reducing substrate bowing.

Abstract: Methods are provided to fabricate semiconductor devices, e.g., FinFET devices, having fin channel structures formed of silicon-germanium alloy layers with uniform thickness. For example, a method includes forming a semiconductor fin structure having sidewalls that define a first width of the semiconductor fins structure, and a hard mask layer disposed on a top surface of the semiconductor fin structure. Portions of the sidewalls are etched to form recessed sidewalls that define a thinned portion, wherein a distance between the recessed sidewalls defines a second width of the thinned portion of the semiconductor fin structure, which is less than the first width. Facetted semiconductor alloy layers are formed on the recessed sidewalls, and then anisotropically etched using the hard mask layer as an etch mask to form planarized semiconductor alloy layers of uniform thickness on the recessed sidewalls of the thinned portion of the semiconductor fin structure.

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.

Abstract: Carbon-doped germanium stressor regions are formed in an nFET device region of a germanium substrate and at a footprint of a functional gate structure. The carbon-doped germanium stressor regions are formed by an epitaxial growth process utilizing monomethylgermane (GeH3—CH3) as the carbon source. The carbon-doped germanium stressor regions that are provided yield more strain in less volume since a carbon atom is much smaller than a silicon atom.

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract: A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device.

Abstract: A substrate holder assembly for use in a controlled spalling process is provided. The substrate holder assembly includes a base structure having a surface in which a base substrate or other work piece can be placed thereupon. A framing element is located above and spaced apart from the surface of the base structure. The framing element has a window which exposes an upper surface of the base substrate and defines an area of the upper surface of the base substrate in which another material can be applied thereto. A support structure containing at least one mechanical securing element is located on the framing element. The support structure mechanically constrains the base substrate within the substrate holder assembly. Each mechanical securing element contacts at least one surface of the support structure and, optionally, one surface of the base substrate.

Abstract: Techniques for integrating spalling into layer transfer processes involving optical device semiconductor materials are provided. In one aspect, a layer transfer method for an optical device semiconductor material includes forming the optical device semiconductor material on a first substrate; depositing a metal stressor layer on top of the optical device semiconductor material; attaching a first handle layer to the metal stressor layer; removing the optical device semiconductor material from the first substrate by pulling the first handle layer away from the first substrate; attaching a second handle layer to the optical device semiconductor material; removing the first handle layer from the stack; and forming a second substrate on the stressor layer. Vertical LED devices and techniques for formation thereof are also provided.

Abstract: A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first semiconducting material layer comprising an element in a first concentration; and forming a second fin in a second semiconducting material layer disposed over the substrate and adjacent to the first semiconducting material layer, the second semiconducting material layer comprising the element in a second concentration; wherein the first concentration is different than the second concentration.

Abstract: A semiconductor structure containing a multiple threshold voltage III-V device is provided. The III-V device includes a III-V compound semiconductor core portion and a III-V compound semiconductor shell portion. The III-V compound semiconductor core and shell portions are virtually defect-free. The III-V compound semiconductor core portion of the III-V device is used for back-gating to achieve multiple threshold voltages. The III-V compound semiconductor shell portion of the III-V device is used as a channel material for a field effect transistor.

Abstract: A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first semiconducting material layer comprising an element in a first concentration; and forming a second fin in a second semiconducting material layer disposed over the substrate and adjacent to the first semiconducting material layer, the second semiconducting material layer comprising the element in a second concentration; wherein the first concentration is different than the second concentration.

Abstract: A light emitting diode (LED) containing device including a light emitting diode (LED) structure, and a light transmissive substrate in contact with the LED structure. The light transmissive substrate has a texture surface tuned to include features with dimensions greater than a wavelength of light produced by the LED structure. In some embodiments, increasing the feature size of the texture to be comparable to the wavelength of light produced by the LED increases light extraction from the LED in comparison to when the feature size of the texture is substantially less or substantially larger than the wavelength of light.