Abstract: Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

Abstract: In one embodiment, a device is described. The device includes a material defining a reaction region. The device also includes a plurality of chemically-sensitive field effect transistors have a common floating gate in communication with the reaction region. The device also includes a circuit to obtain respective output signals from the chemically-sensitive field effect transistors indicating an analyte within the reaction region.

Abstract: Circuitry for ultrasound devices is described. A multilevel pulser is described, which can provide bipolar pulses of multiple levels. The multilevel pulser includes a pulsing circuit and pulser and feedback circuit. Symmetric switches are also described. The symmetric switches can be positioned as inputs to ultrasound receiving circuitry to block signals from the receiving circuitry.

Abstract: System and methods for optical power distribution to a large numbers of sample wells within an integrated device that can analyze single molecules and perform nucleic acid sequencing are described. The integrated device may include a grating coupler configured to receive an optical beam from an optical source and optical splitters configured to divide optical power of the grating coupler to waveguides of the integrated device positioned to couple with the sample wells. Outputs of the grating coupler may vary in one or more dimensions to account for an optical intensity profile of the optical source.

Abstract: Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: A system comprising a multi-modal ultrasound probe configured to operate in a plurality of operating modes associated with a respective plurality of configuration profiles; and a computing device coupled to the handheld multi-modal ultrasound probe and configured to, in response to receiving input indicating an operating mode selected by a user, cause the multi-modal ultrasound probe to operate in the selected operating mode.

Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.

Abstract: A processing device is coupled to a single ultrasound device having a single array of capacitive micromachined ultrasound transducers (CMUTs). The processing device generates a graphical user interface (GUI) having user selectable GUI menu options corresponding to respective ultrasound operating modes for the single ultrasound device having the single ultrasound transducer array. The user-selectable GUI menu options include GUI menu options labeled as representing an ultrasound operating mode for musculoskeletal imaging, breast imaging, carotid imaging, vascular imaging, and abdominal imaging, respectively. The processing device further receives, via the GUI, user input indicating selection of one of the ultrasound operating modes, and in response to receiving the user input, provides an indication to the single ultrasound device having the single array of CMUTs to operate in the selected ultrasound operating mode.

Abstract: An ultrasound-on-a-chip device has an ultrasonic transducer substrate with plurality of transducer cells, and an electrical substrate. For each transducer cell, one or more conductive bond connections are disposed between the ultrasonic transducer substrate and the electrical substrate. Examples of electrical substrates include CMOS chips, integrated circuits including analog circuits, interposers and printed circuit boards.

Abstract: A variable-current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied. The variable-current trans-impedance amplifier may include multiple stages, including a first stage having N-P transistor pairs configured to receive an input signal and produce a single-ended amplified signal.

Abstract: An ultrasound transducer device includes: a first insulating layer formed on a first integrated circuit substrate; a second insulating layer formed on the first insulating layer; a third insulating layer formed on the second insulating layer, and a second substrate bonded to the first integrated circuit. A first cavity is formed in the third insulating layer. The second substrate is bonded to the first integrated circuit such that the first cavity is sealed.

Abstract: A method of forming an ultrasound transducer device includes bonding a membrane to a substrate so as to form a sealed cavity between the membrane and the substrate. An exposed surface located within the sealed cavity includes a getter material that is electrically isolated from a bottom electrode of the cavity.

Abstract: An ultrasonic transducer device includes a patterned film stack disposed on first regions of a substrate, the patterned film stack including a metal electrode layer and a bottom cavity layer formed on the metal electrode layer. The ultrasonic transducer device further includes a planarized insulation layer disposed on second regions of the substrate layer, a cavity formed in a membrane support layer and a CMP stop layer, the CMP stop layer including a top layer of the patterned film stack and the membrane support layer formed over the patterned film stack and the planarized insulation layer. The ultrasonic transducer device also includes a membrane bonded to the membrane support layer. The CMP stop layer underlies portions of the membrane support layer but not the cavity.

Abstract: A method of forming an ultrasonic transducer device involves depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.

Abstract: Ultrasound devices and methods are described, including a repeatable ultrasound transducer probe having ultrasonic transducers and corresponding circuitry. The repeatable ultrasound transducer probe may be used individually or coupled with other instances of the repeatable ultrasound transducer probe to create a desired ultrasound device. The ultrasound devices may optionally be connected to various types of external devices to provide additional processing and image rendering functionality.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes a charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.