Abstract: Systems, methods, and apparatus for space surveillance are disclosed herein. In one or more embodiments, the disclosed method involves scanning, by at least one sensor on at least one satellite in super-geostationary earth orbit (super-GEO), a raster scan over a field of regard (FOR). In one or more embodiments, the scanning is at a variable rate, which is dependent upon a target dwell time for detecting a target of interest. In at least one embodiment, the target dwell time is a function of a characteristic brightness of the target.

Abstract: Systems, methods, and apparatus for space surveillance are disclosed herein. In one or more embodiments, the disclosed method involves scanning, by at least one sensor on at least one satellite in inclined super-geostationary earth orbit (super-GEO), a raster scan over a field of regard (FOR). In one or more embodiments, the scanning is at a variable rate, which is dependent upon a target dwell time for detecting a target of interest. In at least one embodiment, the target dwell time is a function of a range from at least one sensor to the target of interest and a function of a solar phase angle. In some embodiments, the axis of inclination of the inclined super-GEO is a function of the solar phase angle.

Abstract: Systems, methods, and apparatus for space surveillance are disclosed herein. In one or more embodiments, the disclosed method involves scanning, by at least one sensor on at least one satellite in inclined super-geostationary earth orbit (super-GEO), a raster scan over a field of regard (FOR). In one or more embodiments, the scanning is at a variable rate, which is dependent upon a target dwell time for detecting a target of interest. In at least one embodiment, the target dwell time is a function of a range from at least one sensor to the target of interest and a function of a solar phase angle. In some embodiments, the axis of inclination of the inclined super-GEO is a function of the solar phase angle.

Abstract: Systems, methods, and apparatus for space surveillance are disclosed herein. In one or more embodiments, the disclosed method involves scanning, by at least one sensor on at least one satellite in super-geostationary earth orbit (super-GEO), a raster scan over a field of regard (FOR). In one or more embodiments, the scanning is at a variable rate, which is dependent upon a target dwell time for detecting a target of interest. In at least one embodiment, the target dwell time is a function of a characteristic brightness of the target.

Abstract: A board game is provided for a plurality of players comprising a game board including an innermost circle, a plurality of identical player domains, one for each player, a plurality of level regions, an aggregate of aggregated numbers of blank spaces defined in each of the player domains, and indicia for designating the level regions, and for identifying the player domains. The game further includes randomizing means including a plurality of dice having color coded surfaces, symbols, and/or graphic indicia imprinted thereon, question and answer cards indicating varying degrees of difficulty corresponding to the level regions, and a dice cup. Players roll the dice and ask and answer questions in turn to be first to earn an aggregate of first game pieces and place a second game piece on the innermost circle to end the game.

Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Abstract: A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

Abstract: A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit.

Abstract: A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract: A system for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

Abstract: A method of operating a transmission of a vehicle. The method includes determining an open loop ratio percentage from an engine RPM input signal and a brake input signal using a first algorithm. Determining a closed loop ratio percentage from the engine RPM input signal, a vehicle RPM input signal and a throttle input signal using a second algorithm. Summing the open loop percentage and closed loop ratio percentage to calculate a ratio command percentage that is used to sum with a swashplate input to actuate a swashplate positioner and operate the transmission.

Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.

Abstract: A method of operating a vehicle with a hydrostatic circuit. The method includes providing a hydrostatic circuit having first and second hydraulic kits that are fluidly connected to one another by first and second fluid lines. A by-pass valve is placed between the first and second hydraulic lines and is controlled in order to actuate the by-pass valve when certain predetermined conditions are present in order to relieve pressure within the hydrostatic circuit.

Abstract: A system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit.

Abstract: A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

Abstract: A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract: A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit.

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.