Patents by Inventor Keizo Morita
Keizo Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11043252Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.Type: GrantFiled: June 30, 2020Date of Patent: June 22, 2021Assignee: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITEDInventor: Keizo Morita
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Publication number: 20200335148Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Keizo Morita
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Patent number: 10803910Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.Type: GrantFiled: July 12, 2019Date of Patent: October 13, 2020Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Keizo Morita
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Publication number: 20200035273Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.Type: ApplicationFiled: July 12, 2019Publication date: January 30, 2020Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Keizo Morita
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Patent number: 9401192Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.Type: GrantFiled: September 5, 2014Date of Patent: July 26, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masaki Okuda, Keizo Morita, Tomohisa Hirayama
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Patent number: 9190136Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.Type: GrantFiled: September 12, 2014Date of Patent: November 17, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tomohisa Hirayama, Keizo Morita, Naoharu Shinozaki
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Publication number: 20150109875Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.Type: ApplicationFiled: September 5, 2014Publication date: April 23, 2015Inventors: Masaki Okuda, Keizo Morita, Tomohisa Hirayama
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Publication number: 20150098263Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.Type: ApplicationFiled: September 12, 2014Publication date: April 9, 2015Inventors: Tomohisa HIRAYAMA, Keizo Morita, Naoharu Shinozaki
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Patent number: 8542041Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.Type: GrantFiled: April 6, 2010Date of Patent: September 24, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Mitsuhiro Ogai, Hirokazu Yamazaki, Keizo Morita, Kazuaki Yamane, Yasuhiro Fujii, Kazuaki Takai, Shoichiro Kawashima
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Patent number: 8064241Abstract: A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.Type: GrantFiled: October 21, 2009Date of Patent: November 22, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Keizo Morita, Kenichi Nakabayashi
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Publication number: 20100253419Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.Type: ApplicationFiled: April 6, 2010Publication date: October 7, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Mitsuhiro OGAI, Hirokazu Yamazaki, Keizo Morita, Kazuaki Yamane, Yasuhiro Fujii, Kazuaki Takai, Shoichiro Kawashima
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Patent number: 7729181Abstract: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.Type: GrantFiled: January 17, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Keizo Morita, Shoichiro Kawashima
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Publication number: 20100039851Abstract: A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.Type: ApplicationFiled: October 21, 2009Publication date: February 18, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Keizo Morita, Kenichi Nakabayashi
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Publication number: 20090168577Abstract: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.Type: ApplicationFiled: March 5, 2009Publication date: July 2, 2009Applicant: FUJITSU LIMITEDInventors: Keizo Morita, Shoichiro Kawashima
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Patent number: 7525846Abstract: A memory device includes a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.Type: GrantFiled: July 13, 2006Date of Patent: April 28, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Keizo Morita, Shoichiro Kawashima
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Patent number: 7483287Abstract: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.Type: GrantFiled: April 26, 2007Date of Patent: January 27, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Isao Fukushi, Keizo Morita, Shoichiro Kawashima
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Publication number: 20080055960Abstract: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.Type: ApplicationFiled: January 17, 2007Publication date: March 6, 2008Inventors: Keizo Morita, Shoichiro Kawashima
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Publication number: 20070217250Abstract: There is provided a memory device including a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.Type: ApplicationFiled: July 13, 2006Publication date: September 20, 2007Inventors: Keizo Morita, Shoichiro Kawashima
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Publication number: 20070195579Abstract: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.Type: ApplicationFiled: April 26, 2007Publication date: August 23, 2007Inventors: Isao Fukushi, Keizo Morita, Shoichiro Kawashima
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Patent number: 7227769Abstract: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.Type: GrantFiled: March 7, 2005Date of Patent: June 5, 2007Assignee: Fujitsu LimitedInventors: Isao Fukushi, Keizo Morita, Shoichiro Kawashima