Patents by Inventor Keizo Morita
Keizo Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7180766Abstract: The semiconductor memory has word lines; normal memory cells each having a storage capacitor; normal bit lines connected to the normal memory cells; a reference memory cell having a capacitor storing prescribed data; and a reference bit line connected to the reference memory cell. When a word line is selected, the potential of normal bit lines and of reference bit line changes according to the charge on the storage capacitors and on the reference capacitor. A current mirror circuit is also provided, which has a first transistor drain of which is connected to the reference bit line and second transistors drains of which are respectively connected to normal bit lines, the gates of the first and second transistors being connected in common to the reference bit line. Thus even though the capacitance values of ferroelectric capacitors is scattered, the scattering in bit line potentials during read operations can be prevented.Type: GrantFiled: June 17, 2005Date of Patent: February 20, 2007Assignee: Fujitsu LimitedInventor: Keizo Morita
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Publication number: 20060146625Abstract: The semiconductor memory has word lines; normal memory cells each having a storage capacitor; normal bit lines connected to the normal memory cells; a reference memory cell having a capacitor storing prescribed data; and a reference bit line connected to the reference memory cell. When a word line is selected, the potential of normal bit lines and of reference bit line changes according to the charge on the storage capacitors and on the reference capacitor. A current mirror circuit is also provided, which has a first transistor drain of which is connected to the reference bit line and second transistors drains of which are respectively connected to normal bit lines, the gates of the first and second transistors being connected in common to the reference bit line. Thus even though the capacitance values of ferroelectric capacitors is scattered, the scattering in bit line potentials during read operations can be prevented.Type: ApplicationFiled: June 17, 2005Publication date: July 6, 2006Inventor: Keizo Morita
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Patent number: 6970274Abstract: A display device has a display section having scanning lines, and first and second scanning drivers having output lines for supplying scanning signals to the two ends of the scanning lines in the display section. When the potential of at least one of the output lines of the first or second scanning driver is fixed or unfixed due to an error in the first or second scanning driver, the output line at the fixed or unfixed potential is disconnected from the corresponding scanning line in the display section.Type: GrantFiled: January 31, 2001Date of Patent: November 29, 2005Assignee: Sharp Kabushiki KaishaInventors: Keizo Morita, Ken-ichi Nakabayashi
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Publication number: 20050195639Abstract: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.Type: ApplicationFiled: March 7, 2005Publication date: September 8, 2005Inventors: Isao Fukushi, Keizo Morita, Shoichiro Kawashima
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Patent number: 6807082Abstract: A stacked FeRAM uses a structure where the bit line is formed above the ferroelectric capacitor. The word line is formed so that it moves away from the opposing other word line in areas near the contact plug with the relevant contact plug in between, and moves toward the other word line in areas not near the contact plug, and the contact hole is formed so that it is displaced alternately with respect to the longitudinal centerline of the relevant plate line.Type: GrantFiled: October 29, 2002Date of Patent: October 19, 2004Assignee: Fujitsu LimitedInventors: Masaki Aoki, Keizo Morita
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Patent number: 6659845Abstract: A grinding method, in which the grinding operation is performed on a plurality of workpieces having different thicknesses with an end surface in the thickness direction of each workpiece being a surface to be ground, includes the steps of holding the workpieces with a holder such that the surfaces to be ground of the individual workpieces are aligned in the same plane, and grinding the surfaces to be ground of the workpieces while the workpieces are held by the holder. An electronic component provided with an element ground by the grinding method, and a variable capacitor provided with an element ground by the grinding method are also disclosed.Type: GrantFiled: January 12, 2001Date of Patent: December 9, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiromichi Takeda, Hiroyuki Kishishita, Hidetoshi Kita, Keizo Morita
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Patent number: 6639634Abstract: A liquid crystal display device has: a first substrate having an insulating surface; a display unit disposed in a central area of the first substrate and including a plurality of pixels disposed in a matrix shape, a plurality of scan lines for activating pixels disposed in a row direction, and a plurality of signal lines each for transferring video data to an activated pixel among pixels disposed in a column direction; a scan line driver circuit formed in a first row direction side area of a peripheral area of the first substrate outside of the display unit, the scan line driver circuit generating a signal for driving the scan lines; a signal line driver circuit formed in a first column direction side area of the peripheral area of the first substrate, the signal line driver circuit generating a signal for driving the signal lines; and a repair circuit formed in a partial area of the peripheral area of the first substrate, the repair circuit having substantially a same structure as a portion of the scan lineType: GrantFiled: January 26, 2000Date of Patent: October 28, 2003Assignee: Fujitsu Display Technologies CorporationInventors: Hongyong Zhang, Keizo Morita
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Publication number: 20030173604Abstract: According to the present invention, the stacked FeRAM uses a structure where the bit line is formed above the ferroelectric capacitor. The word line is formed so that it moves away from the opposing other word line in areas near the contact plug with the relevant contact plug in between, and moves toward the other word line in areas not near the contact plug, and the contact hole is formed so that it is displaced alternately with respect to the longitudinal centerline of the relevant plate line.Type: ApplicationFiled: October 29, 2002Publication date: September 18, 2003Applicant: FUJITSU LIMITEDInventors: Masaki Aoki, Keizo Morita
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Patent number: 6549250Abstract: In the semiconductor integrated circuit, an auxiliary conductor is formed in a wiring layer beneath a signal wire which connects a position Vin estimated to generate static electricity and a position Vout to be protected from static electricity. The capacitance of a glass substrate can be reduced to {fraction (1/1000)} of the capacitance of the interlayer insulating film. Accordingly, even if a voltage of 1000 to 2000 V is generated between a substrate conveying system and the auxiliary conductor, the glass substrate works as a dielectric, and the voltage generated between the auxiliary conductor and signal wire is only several volts.Type: GrantFiled: February 15, 2001Date of Patent: April 15, 2003Assignee: Fujitsu Display Technologies CorporationInventor: Keizo Morita
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Publication number: 20020075248Abstract: A display device has a display section having scanning lines, and first and second scanning drivers having output lines for supplying scanning signals to the two ends of the scanning lines in the display section. When the potential of at least one of the output lines of the first or second scanning driver is fixed or unfixed due to an error in the first or second scanning driver, the output line at the fixed or unfixed potential is disconnected from the corresponding scanning line in the display section.Type: ApplicationFiled: January 31, 2001Publication date: June 20, 2002Applicant: FUJITSU LIMITEDInventors: Keizo Morita, Ken-ichi Nakabayashi
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Patent number: 6323918Abstract: A capacitor electrode is formed simultaneously with drain bus lines. This capacitor electrode is electrically connected to the contact of two TFT's through the medium of a contact hole. Then, an interlayer insulating film is formed on the entire face and a black matrix of such light blocking metal film as Ti is formed on the interlayer insulating film so as to overlie the channel parts and the contacts of the TFT's and the capacitor electrode. The capacitor electrode, the interlayer insulating film formed thereon, and the black matrix jointly form a capacitor.Type: GrantFiled: December 8, 1997Date of Patent: November 27, 2001Assignee: Fujitsu LimitedInventors: Koji Yoshioka, Masafumi Itokazu, Keizo Morita, Munehiro Haraguchi, Mitsuharu Nakazawa, Hiroshi Murakami
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Publication number: 20010041510Abstract: A grinding method, in which the grinding operation is performed on a plurality of workpieces having different thicknesses with an end surface in the thickness direction of each workpiece being a surface to be ground, includes the steps of holding the workpieces with a holder such that the surfaces to be ground of the individual workpieces are aligned in the same plane, and grinding the surfaces to be ground of the workpieces while the workpieces are held by the holder. An electronic component provided with an element ground by the grinding method, and a variable capacitor provided with an element ground by the grinding method are also disclosed.Type: ApplicationFiled: January 12, 2001Publication date: November 15, 2001Inventors: Hiromichi Takeda, Hiroyuki Kishishita, Hidetoshi Kita, Keizo Morita
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Publication number: 20010020547Abstract: In the semiconductor integrated circuit, an auxiliary conductor is formed in a wiring layer beneath a signal wire which connects a position Vin estimated to generate static electricity and a position Vout to be protected from static electricity. The capacitance of a glass substrate can be reduced to 1/1000 of the capacitance of the interlayer insulating film. Accordingly, even if a voltage of 1000 to 2000 V is generated between a substrate conveying system and the auxiliary conductor, the glass substrate works as a dielectric, and the voltage generated between the auxiliary conductor and signal wire is only several volts.Type: ApplicationFiled: February 15, 2001Publication date: September 13, 2001Applicant: FUJITSU LIMITEDInventor: Keizo Morita
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Patent number: 6064222Abstract: A liquid-crystal display device includes a substrate with a pixel area including a plurality of scanning buses, a plurality of data buses intersecting therewith and pixel transistors and pixel electrodes formed at the intersections therebetween; a scanning driver for energizing these scanning buses; and a data driver for presenting these data buses with data signals. A checkout circuit equipped with a plurality of checkout transistors connected to the corresponding data buses or scanning buses; an input bus for applying prescribed checkout signals to the plurality of checkout transistors; and an output bus for picking up the signals from the plurality of checkout transistors.Type: GrantFiled: August 13, 1997Date of Patent: May 16, 2000Assignee: Fujitsu LimitedInventors: Keizo Morita, Munehiro Haraguchi, Koji Yoshioka, Masafumi Itokazu, Hiroshi Murakami
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Patent number: 6040814Abstract: An active-matrix LCD causes no cross-talk even if the capacitance between a given cell and adjacent data lines is large. The LCD has a liquid crystal panel which has data lines arranged in parallel with one another, scan lines arranged orthogonally to the data lines, and liquid crystal cells arranged at the intersections of the data and scan lines, respectively. Each of the cells has a cell electrode and a switching device that is arranged between and connected to the cell electrode and a corresponding one of the data lines. The conduction of the switching device is controlled in response to a scan pulse applied to a corresponding one of the scan lines. The LCD also has a data driver for applying data signals to the data lines, respectively, so that the data signals are written to corresponding ones of the cells, and a scan driver for applying the scan pulse sequentially to the scan lines.Type: GrantFiled: May 13, 1996Date of Patent: March 21, 2000Assignee: Fujitsu LimitedInventors: Hiroshi Murakami, Koji Yoshioka, Keizo Morita, Masafumi Itokazu, Ken-ichi Nakabayashi, Akira Yamamoto, Munehiro Haraguchi
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Patent number: 4319188Abstract: A magnetic rotary encoder for detecting incremental angular displacement, angular velocity and rotating direction using magneto-resistors is disclosed. A drum, disk or cupshaped rotary member is attachable to a rotatable shaft. A magnetic medium is provided on a surface of the rotary member and is divided at a pitch p into a plurality of magnetic sections each of which has a magnetic signal recorded. The magnetic medium produces an alternating magnetic field as the rotary member revolves. Alternatively, a plurality of permanent magnets are provided on the surface of the rotary member to produce the alternating magnetic field of the rotary member revolves. A magnetic field detector includes at least one magneto-resistor having a stripe-like configuration with width D. The magneto-resistor is located in the vicinity of the rotary member so as to be spaced from the magnetic medium or the permanent magnets by equal to or less than p at its nearest portion and by equal to or less than 20p at its furthest portion.Type: GrantFiled: December 24, 1980Date of Patent: March 9, 1982Assignee: Nippon Electric Co., Ltd.Inventors: Susumu Ito, Morimasa Nagao, Kaoru Toki, Keizo Morita
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Patent number: 4313074Abstract: A digital servo control system is responsive to a command signal indicative of a command position of a moveable element and to a phase modulated signal corresponding to the angle of rotation of a motor controlling said moveable element to develop a motor drive signal to position the motor. The system provides control during a velocity control mode and a position control mode, the latter occurring after the moveable element is moved to a predetermined small incremental distance from the commanded position. During the velocity control mode the motor is driven in accordance with a reference velocity selected in dependence upon the position error signal. Following a prescribed time after entry into the position control mode, the position error has added thereto an integration signal which increases in the same sense as the position error.Type: GrantFiled: April 28, 1980Date of Patent: January 26, 1982Assignee: Nippon Electric Co., Ltd.Inventors: Tadashi Nomura, Hiroshi Inada, Keizo Morita, Akio Watanabe, Kiyoaki Nishikawa