Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation: of a Ramsey Type-II interleaver is realized.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: The present invention provides an SEU immune solution which minimizes the disadvantages of the increased weight and size of prior art SEU immune circuits. In the present invention, the SEU immune solution can comprise two portions. First, a control portion can be comprised of SEU tolerant electronics as described in the prior art. A processor comprises the second portion and is preferably not SEU immune. The present invention makes it unnecessary for both portions of the circuit to be comprised of SEU tolerant logic in order for the output of the present invention to be SEU tolerant. In particular, the present invention is especially well suited for outer space travel since the present invention will not be upset by SEUs and retains a small package size and light weight.

Abstract: A method and apparatus for decoding Reed-Solomon codes in large Galois Fields GF(2.sup.n) represents the finite field as a quadratic extension field of one or more subfields GF(2.sup.m). This type of field representation allows embedded subfields, as well as the primary extension field to be simultaneously represented in normal form. The basic arithmetic operations for the extension field are written solely in terms of operations performed in one or more subfields. The operations of multiplication, inverse, square, square root and conjugation are performed in GF(2.sup.n), utilizing only operations from the subfield GF(2.sup.m).

Abstract: A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current.

Abstract: The preferred embodiment includes a method and apparatus for generating a comma code. A data word having a value m is received. A binary storage apparatus receives the data value. A storage apparatus is coupled to the output of the address calculator. The storage apparatus includes a plurality of single bit storage elements that are arranged to provide an M bit output. Each single bit storage element is initialized to a first value. The address calculator calculates the appropriate single bit storage element to be selectively inverted.

Abstract: A Reed-Solomon Galois Field Euclid algorithm error correction decoder solves Euclid's algorithm with a Euclid stack which can be configured to function as a Euclid divide or a Euclid multiply module. The decorder is able to resolve twice the erasure errors by selecting .GAMMA.(x) and T(x) as the initial conditions for .LAMBDA..sup.(0) (x) and .OMEGA..sup.(0) (x), respectively.

Abstract: A Reed-Solomon Galois Field Euclid algorithm decoder determines whether an error is uncorrectable by checking for:I. deg [.LAMBDA.(x))].ltoreq.tII. deg [.OMEGA.(x)]<deg[.LAMBDA.(x)]III. All roots of .LAMBDA.(x) are in GF(q.sup.m)IV. Roots of .LAMBDA.(x) are distinctV. .LAMBDA.(x) has no roots at 0VI. S(x).LAMBDA.(x)=.ident..OMEGA.(x) mod x.sup.2tAn error in a received Reed Solomon message may be uncorrectable. An error is correctable only when each of the six conditions are met. Any error which fails to meet these six criteria cannot be corrected It is important to users of such encoded data that they are aware that an error is contained therein which is uncorrectable. Because it has only recently been proven that failure to meet these criteria in fact is the result of an uncorrectable error. No prior art Reed Solomon decoder checks to determine whether these criteria are in fact met. Many of these criteria are checked by implication as the normal result of calculating through Euclid's algorithm.