Patents by Inventor Kenichi Yasuda

Kenichi Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147398
    Abstract: A base station includes the following parts: a propagation estimation part that estimates a radio wave propagation characteristic between a terminal and base station based on a training signal received from the terminal; a phase compensation part that compensates data to be transmitted to the terminal with phase rotation of a carrier wave that is indicated by the radio wave propagation characteristic; and a frequency conversion part that transmits the data that has been compensated by the phase compensation part to the terminal.
    Type: Application
    Filed: February 9, 2022
    Publication date: May 2, 2024
    Applicant: National Institute of Information and Communications Technology
    Inventors: Kenichi TAKIZAWA, Satoshi YASUDA, Nobuyasu SHIGA
  • Publication number: 20240119094
    Abstract: This data classification device comprises an acquisition unit, a data classification unit, an output unit, and an input unit. The acquisition unit acquires data to be classified as input data. The data classification unit uses a classification model to estimate the classification of the input data. The output unit outputs display data displaying: an image divided into a plurality of groups based on a group division standard based on the confidence level when the classification model estimates the classification of the input data; and an image for changing the group division standard. The input unit acquires the data for changing the group division standard as an input result. Moreover, the output unit outputs display data in which the classified data is divided into the plurality of groups based on the group division standard indicated by the input result.
    Type: Application
    Filed: December 3, 2021
    Publication date: April 11, 2024
    Applicant: NEC Corporation
    Inventors: Banri ODA, Kenichi Yasuda, Yutong Zhang
  • Publication number: 20230356220
    Abstract: The present disclosure provides a channel device (100, 101, 102, 103, 200, 300, 500, 600, 700) including a flow channel (10) formed of a groove (31) provided in a substrate (30) and a porous membrane (50) having pores (56) communicating in a direction intersecting a thickness direction thereof, in which at least a portion of the porous membrane (50) in contact with the substrate (30) is liquid-tightly sealed along the flow channel (10), and a manufacturing method thereof.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Inventors: Aya MOCHIZUKI, Hiroyuki YUKAWA, Kenichi YASUDA, Takahiro OBA
  • Patent number: 11693620
    Abstract: An information processing apparatus comprises a first acquiring unit configured to acquire a command input to application software, a second acquiring unit configured to acquire scene information representing a scene represented by a screen displayed when executing the application software, a third acquiring unit configured to acquire a command file based on the command and the scene information, and an execution unit configured to execute processing in accordance with the command file.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: July 4, 2023
    Assignee: Humming Heads, Inc.
    Inventors: Naoyuki Oe, Takuma Sugita, Makoto Kurita, Yuichi Yasuda, Shogo Otsuka, Kenichi Yasuda
  • Publication number: 20220228108
    Abstract: There is provided a cell culture base material having a porous membrane having an opening ratio of 30% to 70% and an extracellular matrix with which an inside of a hole of the porous membrane is filled. There is also provided a cell culture base material with cells having a cell layer on at least one surface of the cell culture base material.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Inventors: Keisuke OKU, Daichi HIKIMOTO, Takahiro OBA, Kenichi YASUDA, Hiroyuki YUKAWA
  • Patent number: 11213945
    Abstract: A robot simulator includes a storage device that stores model information related to the robot and an obstacle in the vicinity of the robot, and an acquisition device that obtains first input information defining a start position and an end position of operation of the robot. A processing device generates a path for moving the distal end portion of the robot from the start position to the end position while avoiding collisions between the robot and the obstacle based on the first input information and the model information. The processing device also generates image data including an illustration of the obstacle and an index indicating a via-point of the path.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: January 4, 2022
    Inventors: Koichi Kuwahara, Yoshifumi Onoyama, Kenichi Yasuda, Wataru Watanabe
  • Patent number: 11200945
    Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: December 14, 2021
    Assignee: ZENTEL JAPAN CORPORATION
    Inventors: Takashi Kubo, Masaru Haraguchi, Takeshi Hamamoto, Kenichi Yasuda, Yasuhiko Tsukikawa, Hironori Iga
  • Patent number: 11123864
    Abstract: A motion teaching apparatus includes a teaching motion detection device, a demonstration tool, and circuitry. A robot includes a leading end to move in a first coordinate system. A teaching motion detection device detects a position of the demonstration tool in a second coordinate system. The circuitry derives a relationship between the first and second coordinate system based on a position of the demonstration tool in the first coordinate system at at least one spot and based on the position of the demonstration tool in the second coordinate system at the at least one spot; obtains a transition of the position of the demonstration tool during the demonstration using the demonstration tool; and generates a motion command to control motion of the leading end of the robot based on the transition and the coordinate system relationship information.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 21, 2021
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Toshihiro Iwasa, Ryoichi Nagai, Nathanael Mullennix, Shingo Ando, Kenichi Yasuda
  • Patent number: 10991418
    Abstract: A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: April 27, 2021
    Assignee: ZENTEL JAPAN CORPORATION
    Inventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
  • Publication number: 20200293275
    Abstract: An information processing apparatus comprises a first acquiring unit configured to acquire a command input to application software, a second acquiring unit configured to acquire scene information representing a scene represented by a screen displayed when executing the application software, a third acquiring unit configured to acquire a command file based on the command and the scene information, and an execution unit configured to execute processing in accordance with the command file.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 17, 2020
    Inventors: Naoyuki OE, Takuma Sugita, Makoto Kurita, Yuichi Yasuda, Shogo Otsuka, Kenichi Yasuda
  • Publication number: 20200135261
    Abstract: According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device.
    Type: Application
    Filed: March 6, 2017
    Publication date: April 30, 2020
    Inventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
  • Publication number: 20200001454
    Abstract: A motion teaching apparatus includes a teaching motion detection device, a demonstration tool, and circuitry. A robot includes a leading end to move in a first coordinate system. A teaching motion detection device detects a position of the demonstration tool in a second coordinate system. The circuitry derives a relationship between the first and second coordinate system based on a position of the demonstration tool in the first coordinate system at at least one spot and based on the position of the demonstration tool in the second coordinate system at the at least one spot; obtains a transition of the position of the demonstration tool during the demonstration using the demonstration tool; and generates a motion command to control motion of the leading end of the robot based on the transition and the coordinate system relationship information.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 2, 2020
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Toshihiro IWASA, Ryoichi NAGAI, Nathanael MULLENNIX, Shingo ANDO, Kenichi YASUDA
  • Publication number: 20190378561
    Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.
    Type: Application
    Filed: January 31, 2017
    Publication date: December 12, 2019
    Inventors: TAKASHI KUBO, MASARU HARAGUCHI, TAKESHI HAMAMOTO, KENICHI YASUDA, YASUHIKO TSUKIKAWA, HIRONORI IGA
  • Publication number: 20180236657
    Abstract: A robot simulator includes a storage device that stores model information related to the robot and an obstacle in the vicinity of the robot, and an acquisition device that obtains first input information defining a start position and an end position of operation of the robot. A processing device generates a path for moving the distal end portion of the robot from the start position to the end position while avoiding collisions between the robot and the obstacle based on the first input information and the model information. The processing device also generates image data including an illustration of the obstacle and an index indicating a via-point of the path.
    Type: Application
    Filed: February 19, 2018
    Publication date: August 23, 2018
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Koichi KUWAHARA, Yoshifumi ONOYAMA, Kenichi YASUDA, Wataru WATANABE
  • Patent number: 9881874
    Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kenichi Yasuda, Shinya Arai
  • Publication number: 20170154852
    Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 1, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi YASUDA, Shinya ARAI
  • Publication number: 20150192704
    Abstract: The method for producing an optical film includes a film-curing step of curing the coating to form a liquid crystal layer by supporting a second surface of the transparent support by a back-up roller while heating, and irradiating the coating with ultraviolet light, wherein, when an reaching temperature of the transparent support in curing of the coating is set to 80° C. or higher, and P [N/m2] represents a surface pressure, T [N] represents a tensile force applied to the transparent support, R [m] represents a radius of the back-up roller, L [m] represents a width of the transparent support, and G [GPa] represents an elastic modulus in a width direction of the transparent support at the reaching temperature of the transparent support in curing of the coating, Expression (1): P=T/RL and Expression (2): P>69/(G?1.5)+400 are satisfied.
    Type: Application
    Filed: January 5, 2015
    Publication date: July 9, 2015
    Applicant: FUJIFILM Corporation
    Inventors: Kenichi YASUDA, Hiroyuki YUKAWA, Yuki SAIKI
  • Patent number: D1016031
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda
  • Patent number: D1016032
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda
  • Patent number: D1016033
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda