Abstract: Construction machine including: an inverter; a battery; a battery controller; a main controller controlling the inverter based on limited power modes prescribed; and a display device displaying a remaining battery electric power. The main controller calculates open circuit voltage and battery resistance values of the battery at the state of energy of the battery based on the specification information about the battery and state of energy of the battery which are input from the battery controller, calculates an amount of electric power stored in the battery in each of the limited power modes based on the open circuit voltage value and battery resistance value of the battery as well as limited power and operating voltage prescribed for each of the limited power modes, and outputs a display signal for displaying the amount of electric power stored in the battery in each of the limited power.

Abstract: An electric power storage device (19) disposed on a revolving frame (6) located closer to an upstream side in a flow direction of cooling air (F) than a heat exchanger (18) is provided on an upper revolving structure (4). The electric power storage device (19) has a box-shaped casing (20) forming an outer wall and a battery module (29) provided in the casing (20) and accommodating an electrolyte. An electrolyte discharge pipe (30) for discharging an electrolyte mist and/or electrolyte injected out of the battery module (29) at abnormality of the battery module (29) to an outside of the upper revolving structure (4) is provided on the casing (20).

Abstract: A semiconductor storage device includes at least one memory from among a primary memory, a minor memory storing data corresponding to data stored in the primary memory, and a buffer memory; and a controller that controls the at least one memory so as to store data in the at least one memory and read data from the at least one memory.

Abstract: There are provided a work vehicle comprising a motor generator (6) driven by an engine, a hydraulic pump (4) driven by at least either of the motor generator and the engine, a work device (50) driven by hydraulic fluid from the hydraulic pump, a electric traction motor (9) driving wheels (61), an electrical storage device (11) connected to the motor generator and to the electric traction motor and charged electrically on the basis of a target SOC; and a control device (200) varying the target SOC for the electrical storage device (11) on the basis of total demanded power (Pf+Prun) of the hydraulic pump and the electric traction motor.

Abstract: To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device includes a memory including at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other. An object of the present invention is to improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element.

Abstract: To reduce deterioration of non-volatile memory and write data at higher speed, writing data is stored in a ReRAM when a page utilization rate R is lower than a threshold Rth1 and/or the writing data is frequently-rewritten data. With an empty space Semp2 in the ReRAM being less than a threshold Sth (step S110), when the data in the ReRAM is infrequently-rewritten data and the page utilization rate R obtained if target data is stored in a flash memory 22 is equal to or higher than a threshold value Rth3 (steps S120 and S130), data of logical sectors contained in N logical page addresses stored in a transfer list is read from the ReRAM to be written to the flash memory (steps S140 to S160). These steps reduce deterioration of the flash memory and allow higher data writing.

Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

Abstract: The SSD performs to encode input data from the host device into BCH code having data length and code length sequentially and controls RRAM to stores the encoded data when the write requesting signal is input from the host device. When the number of BCH code that becomes data of one page of the flash memory after being decoded is stored to RRAM, the SSD controls RRAM to read out data stored in RRAM, performs error correction and decoding to the read data as BCH code having the data length and the code length, and controls the flash memory to store the encoded data.

Abstract: When a data utilization ratio R which is a utilization ratio of sectors in one page is not lower than a threshold value Rth1 and when write data is not frequently-rewritten data, a flash memory is controlled such that the write data is stored into the flash memory. When the data utilization ratio R which is the utilization ratio of sectors in one page is lower than the threshold value Rth1 or when the write data is frequently-rewritten data although the data utilization ratio R is not lower than the threshold value Rth1, a ReRAM is controlled such that the write data is stored into the ReRAM. This suppresses deterioration of the flash memory.

Abstract: A memory controller sets an estimated cell error ratio CERest based on an estimated retention time Tret obtained from a calculated bit error ratio BER, a number of rewrite times NW/E, data Datatag of a target cell and data Dataadj of memory cells surrounding the target cell, sets an upper-level page LLRu and a lower-level page LLRl with regard to all bits of read-out one-page data using the set estimated cell error ratio CERest and performs error correction and decoding of data read out from a flash memory using the settings of the upper-level page LLRu and the lower-level page LLRl. This improves the error correction capability, while suppressing an increase in processing time.

Abstract: A construction machine is provided with management units (11, 12) configured to control the construction machine based on a plurality of limited power modes prescribed to control the output of a battery pack (18), and calculate an amount of electric power stored in the battery pack in each of the limited power modes based on specification information about the battery pack, on the state of charge of the battery pack, and on limited power and an operating voltage prescribed for each of the limited power modes; and a display device (14) configured to display the amount of electric power in each of the limited power modes based on the amount of electric power calculated by the management units. This allows the amount of electric power in the unselected limited power modes to be displayed and facilitates battery replacement work.

Abstract: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Abstract: The interposer 30 is disposed on an upper surface of the stacked structure 24 formed by stacking a plurality of a DRAM chip 20 and a plurality of a flash memory chip 22. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit 40. Thus down-size of the entire device is accomplished.

Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

Abstract: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Abstract: When detected number of errors data Nerror exceeds the upper limit number of errors Nmax, an error correction circuit of a memory controller stores twice as long data length as stored data length for execution Sdata as the data length for execution Sdata in a correction information memory unit, and code length Scref longer than the data length for execution Sdata and detectable more errors than the upper limit number of errors as the code length for execution Scode in the correction information memory unit 32 (step S100 and S110). The error correction circuit encodes input data using BCH code having the stored code length for execution Scode, stored encoded data in a semiconductor memory device, is input data stored in the semiconductor memory device, performs error correction for input data using BCH code, and decode error corrected data.

Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Abstract: When write data D is high rewritten data, a PC 10 controls a DRAM 24 to store the write data D (steps S100 and S110). When the write data D is not the high rewritten data, the PC 10 outputs an RRAM write request signal and the write data D to an SSD (step S100 and S120). A memory controller of the SSD input the RRAM write request signal controls the RRAM and an SRAM to store the write data D in the RRAM or the SRAM. This treatment enables data stored in the DRAM to be rewritten frequently. Therefore, the decrease of number of times of refresh operation of the DRAM and the decrease of power consumption are accomplished.

Abstract: When write request signal is input from a host device, an SSD inputs data input from the host device in an encoder sequentially and controls a RRAM to store data output from the encoder. When size of data stored in the RRAM reaches predetermined size Sref, the SSD controls the RRAM to read out data of size of the predetermined size Sref, inputs read data from the RRAM in the encoder, and controls a flash memory to store data output from the encoder. This configuration accomplishes the increase of the data write speed and improvement of reliability of the data.

Abstract: The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.