Abstract: A power converting apparatus generates a carrier having a waveform in which an absolute value of a slope is constant with respect to time, based on a value for internally dividing amplitude of the waveform into first and second values. Commutation of a converter is performed when the carrier takes a reference. Adoption is allowed of a zero voltage vector as a switching mode of an inverter in a period in which the carrier takes a first command value to a second command value. A value for internally dividing a value from the reference to a maximum value of the carrier at a ratio between a third value and a fourth value is the first command value. A value for internally dividing a value from a minimum value of the carrier to the reference at a ratio between the third value and the fourth value is the second command value.

Abstract: A semiconductor memory device having two refreshment modes of auto-refreshment and partial self-refreshment imposed on memory cells includes a command decoder which detects one of the refreshment modes from an input command, outputs type data which indicates the detected refreshment mode, and outputs a refreshment signal which indicates the start of refreshment; a mode register in which the type data is set; a signal selection circuit which determines whether or not the refreshment signal is to be delayed, in accordance with the type data set in the mode register, and outputs the refreshment signal, which is delayed or not delayed in accordance with the result of the determination, as a refreshment start signal; and a control circuit which reads the type data set in the mode register based when receiving the refreshment start signal, and performs refreshment corresponding to the type data.

Abstract: A power module that converts a dc voltage into a three-phase ac voltage, current sensors that detect the ac side current of the power module, a shunt resistor and an amplifier that detect a dc side current of the power module, and a control section that controls the power module by pulse-width modulation using a spatial vector modulation method on the basis of the ac side current detected by the current sensors and the dc side current detected by the shunt resistor and the amplifier are provided. The control section corrects the amplitude and the offset of the ac side current detected by the current sensors on the basis of current components, corresponding to current components of prescribed phases of the ac side current, of the dc side current detected by the shunt resistor and the amplifier.

Abstract: A current control type converter has a converter section and a control section that includes three controllers. A first controller calculates and outputs an active current instruction value by proportional-plus-integral control to perform proportional integration of a deviation between the value of a DC voltage outputted from the converter section and a DC voltage instruction value. A second controller calculates and outputs an active voltage correction value by proportional-plus-integral control to perform proportional integration of a deviation between the active current instruction value from the first controller and the value of an active current inputted to the converter section. A third controller calculates and outputs a reactive voltage correction value by proportional-plus-integral control to perform proportional integration of a deviation between the value of a reactive current inputted to the converter section and a reactive current instruction value.

Abstract: In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion (20) including a chip (21) made of wide band gap semiconductor and a member (22, 23) having a heat resistant temperature equal to or higher than that of the chip (21); and a peripheral component (25) arranged in the vicinity of the chip portion (20) and having a heat resistant temperature lower than that of the chip (21). The chip (21) and the peripheral component (25) are thermally insulated from each other so that the temperature of the peripheral component (25) does not exceed the heat resistant temperature of the peripheral component (25).

Abstract: An output voltage command signal for outputting a specified three-phase ac output voltage is generated by a line voltage control command signal generating section, and a signal representing a current flow ratio is generated by a current flow ratio generating section based on a specified input current command signal. The output voltage command signal is corrected by a command signal computing section based on the output voltage command signal generated by the line voltage control command signal generating section and the signal representing the current flow ratio generated by the current flow ratio generating section. A PWM conversion signal is generated by a PWM conversion signal generating section based on the corrected output voltage command signal and a carrier signal. Based on the generated PWM conversion signal, a three-phase ac input voltage is converted into a specified three-phase ac input voltage by a conversion section.

Abstract: A motor control unit (10) includes: a power converter (40) having a rectifier circuit (20) which rectifies an AC voltage from an AC power supply (31), a capacitor circuit (22) which receives an output of the rectifier circuit (20) and outputs a rectified voltage having pulses from both ends of a capacitor (13) and an inverter circuit (25) which receives the rectified voltage and outputs an AC voltage to the motor (30); and a motor controller (41) controlling the motor (30) by controlling the inverter circuit (25). The motor controller (41) performs torque control to vary an output toque of the motor (30) in response to variation in load torque of the motor (30).

Abstract: The inverter comprises a diode bridge (21) that rectifies an inputted three-phase AC voltage into a DC voltage, an inverter section (22) that converts the DC voltage converted by the diode bridge (21) into an AC voltage and outputs the resulting voltage, an LC filter that has an inductor Ldc connected between one output terminal of the diode bridge (21) and one input terminal of the inverter section and a capacitor Cdc connected across the input terminals of the inverter section, a voltage detecting section (24) that detects cross terminal voltage of the inductor Ldc, and a control section (100) that controls the inverter section (22). The control section (100) controls the inverter section (22) so that the transfer characteristic of the I/O voltage of the inverter section (22) becomes a characteristic of the first-order lag system on the basis of the cross terminal voltage of the inductor Ldc detected by the voltage detecting section (24).

Abstract: A converter section converts a three-phase ac input voltage into a dc voltage, and an inverter section converts the dc voltage converted by the converter section into a prescribed three-phase ac output voltage. The converter section converts the three-phase ac input voltage into the dc voltage on the basis of trapezoidal waveform voltage instruction signals from a trapezoidal waveform voltage instruction signal generating part and a carrier signal from a carrier signal generating part. The inverter section converts the dc voltage converted by the converter section 1 into a prescribed three-phase ac output voltage on the basis of an inverter section instruction signal corrected by an instruction signal correcting part. The trapezoidal waveform voltage instruction signal generating part generates sloped regions of the trapezoidal waveform voltage instruction signals by using a prescribed table.

Abstract: A semiconductor memory device having two refreshment modes of auto-refreshment and partial self-refreshment imposed on memory cells includes a command decoder which detects one of the refreshment modes from an input command, outputs type data which indicates the detected refreshment mode, and outputs a refreshment signal which indicates the start of refreshment; a mode register in which the type data is set; a signal selection circuit which determines whether or not the refreshment signal is to be delayed, in accordance with the type data set in the mode register, and outputs the refreshment signal, which is delayed or not delayed in accordance with the result of the determination, as a refreshment start signal; and a control circuit which reads the type data set in the mode register based when receiving the refreshment start signal, and performs refreshment corresponding to the type data.

Abstract: A water-absorbing polyurethane foam is produced by reacting, foaming, and curing a raw material which includes aliphatic or alicyclic polyisocyanate, polyester polyol, a polyoxyethylene compound for a hydrophilizing agent, a catalyst and a blowing agent. Thus obtained water-absorbing polyurethane foam has a coating film made from a cured substance of the foam formed on both surfaces. The content of the polyoxyethylene compound in the raw material is 1 to 10 parts by mass with respect to 100 parts by mass in total of the polyester polyol and the polyoxyethylene compound. The raw material is reacted, foamed, and cured at a temperature of 40 to 130° C. The polyisocyanate has an isocyanate index of preferably 85 to 100.

Abstract: Capacitors are connected in series between a first DC link section and a second DC link section when the capacitors are charged by a regenerative current derived from an inverter section. During discharge, as first, second switching circuits turn on, the capacitors are discharged with those capacitors connected in parallel between a first DC link section and a second DC link section.

Abstract: Choppers are provided respectively in the output stages of two diode bridges, and their output sides are connected in parallel to a smoothing capacitor. By controlling the operations of the two choppers, the currents which are allowed to be inputted to the diode bridges are made triangular waves of mutually opposite phases, or middle-phase waveforms of three phases.

Abstract: A capacitor-input type three-phase rectification circuit comprises a three-phase AC power supply (1), a diode rectifier circuit (4), and a low-frequency filter connected between the three-phase AC power supply (1) and the diode rectification circuitry (4), the low frequency filter consisting of AC reactors (2u)(2v)(2w) and ?-connection or Y-connection capacitors (8u)(8v)(8w), so that higher harmonic currents are reduced to be equal to or less than standard values, and that lowering in input power factor and lowering in DC voltage are prevented from occurrence.

Abstract: A semiconductor intergrated circuit device is comprised a main portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A capacitor-input type three-phase rectification circuit comprises a three-phase AC power supply (1), a diode rectifier circuit (4), and a low-frequency filter connected between the three-phase AC power supply (1) and the diode rectification circuitry (4), the low frequency filter consisting of AC reactors (2u)(2v)(2w) and &Dgr;-connection or Y-connection capacitors (8u)(8v)(8w), so that higher harmonic currents are reduced to be equal to or less than standard values, and that lowering in input power factor and lowering in DC voltage are prevented from occurrence.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns and a sub memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns, wherein at least one of address input terminals assigning rows or columns of the main memory portion and at least one of address input terminals assigning rows or columns of the sub memory portion are commonly used and a total number of address input terminals is equal to or smaller than the number of address input terminals assigning rows or columns of the main memory portion. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor memory device includes a plurality of memory cell groups, each of the memory cell groups being selectable by an address signal or an internal control signal and a plurality of registers coupled to a corresponding one of the memory cell groups, each of the registers storing a data input/output mode to set the data input/output mode for the corresponding one of the memory cell groups.

Abstract: A semiconductor integrated circuit device includes a main memory portion, a sub memory portion including a plurality of memory cell groups and a bidirectional data transfer circuit provided between the main memory portion and the sub memory portion. A bi-directional data transfer between an arbitrary area of the main memory portion and the plurality of the memory cell groups, and a read or write operation are performed simultaneously. Therefore, the semiconductor integrated circuit device has a main memory suitable for being accessed from a plurality of memory masters or data processors.