Patents by Inventor Kenji Hamada

Kenji Hamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10110021
    Abstract: There is provided a balancing device that equalizes voltages between storage cells of a battery composed of a plurality of series-connected storage cells or voltages between electrical storage modules composed of a plurality of series-connected storage cells of the battery. The balancing device equalizes voltages between the energy storage modules by transferring electric power between the electrical storage modules through an element to which all of the electrical storage modules are connected, the transferring being realized by on-off control of current supply to each of the electrical storage modules, the on-off control being performed with a first duty cycle. Further, the balancing device introduces a period in which the on-off control is performed with a second duty cycle, the second duty cycle being different from the first duty cycle.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 23, 2018
    Assignee: FDK Corporation
    Inventors: Kenji Hamada, Masatsuru Miyazaki
  • Publication number: 20180188533
    Abstract: A head-up display device includes: an image generator that emits light; and a display member including: a projection surface onto which the light is projected, wherein when the light is emitted to the projection surface, the light is reflected from the projection surface to display a real image passing through the display member and a virtual image; and a plate material including: a pair of optical surfaces, one positioned nearer to an observer side than the other, and either of which can serve as the projection surface; an end surface connecting peripheries of the pair of optical surfaces; and an end main surface formed at a predetermined a distance from the end surface to a reference line passing through a reference point and being orthogonal to a tangent plane at the reference point.
    Type: Application
    Filed: June 20, 2016
    Publication date: July 5, 2018
    Applicant: Konica Minolta, Inc.
    Inventors: Kenji Ogiwara, Kenji Hamada, Shinobu Suga, Yosuke Aoki, Toshiya Takitani
  • Patent number: 10008863
    Abstract: In a balance correction circuit including a plurality of converter type balance correction units that control a supply of a current to a plurality of power storage cells by complementarily on/off controlling two switching elements and hereby allowing to exchange power between or among power storage cells via an inductor to equalize the voltages of the power storage cells, a common timing signal used to generate a control signal of a switching element is supplied to each of the above balance correction units. For example, the balance correction circuit generates a timing signal to supply to a first balance correction unit based on a variation in a voltage applied to the capacitive element charged by a voltage difference created between a control signal generated by the second balance correction unit and a second power storage cell cathode of the balance correction unit.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: June 26, 2018
    Assignee: FDK Corporation
    Inventor: Kenji Hamada
  • Publication number: 20180040410
    Abstract: An isolated switching power supply of the present invention includes: a first circuit board provided with a pattern of a primary winding constituting an isolation transformer; a second circuit board provided with patterns of secondary windings constituting the isolation transformer, wherein a secondary winding pattern portion is arranged to face a primary winding pattern portion of the first circuit board at a predetermined interval; and a core inserted into the primary winding of the first circuit board and the secondary windings of the second circuit board and made of a magnetic body constituting the isolation transformer.
    Type: Application
    Filed: February 25, 2016
    Publication date: February 8, 2018
    Inventors: Kenji Hamada, Tomoyuki Nagayoshi, Tadashi Sato, Norio Fukui
  • Patent number: 9716006
    Abstract: A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 ?m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 25, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Naruhisa Miura, Yosuke Nakanishi
  • Patent number: 9704947
    Abstract: A semiconductor device including a terminal region that can suppress a resist collapse in manufacturing and effectively relieve a concentration of electric fields and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor element formed in a semiconductor substrate made of a silicon carbide semiconductor of a first conductivity type and a plurality of ring-shaped regions of a second conductivity type formed in the semiconductor substrate while surrounding the semiconductor element in plan view. At least one of the plurality of ring-shaped regions includes one or more separation regions of the first conductivity type that cause areas of the first conductivity type on an inner side and an outer side of one of the ring-shaped regions to communicate with each other in plan view.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: July 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Ebihara, Naruhisa Miura, Kenji Hamada, Koji Okuno
  • Patent number: 9687212
    Abstract: According to one embodiment, an ultrasonic diagnosis apparatus executes B-mode scanning and color Doppler mode scanning on a scanning region associated with an interior of the womb of a pregnant woman via an ultrasonic probe. A first generating unit generates first color Doppler mode data and generates first B-mode data. A specifying unit specifies a specific region including at least one of an amniotic fluid region and a fetus region based on one of a signal intensity distribution and a luminance distribution of the first B-mode data. A second generating unit generates second color Doppler mode data by deleting a specific data from the first color Doppler mode data. The specific color Doppler mode data corresponds to the specific region. A display unit displays a color Doppler mode image and a first B-mode image while superimposing the color Doppler mode image and the first B-mode image.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: June 27, 2017
    Assignee: Toshiba Medical Systems Corporation
    Inventors: Kenji Hamada, Yoshitaka Mine
  • Publication number: 20170140934
    Abstract: A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 ?m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).
    Type: Application
    Filed: April 10, 2015
    Publication date: May 18, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji HAMADA, Naruhisa MIURA, Yosuke NAKANISHI
  • Publication number: 20170120343
    Abstract: The cutting device includes a rotating portion for rotating the cutting tool in a rotation axis line of the cutting tool and a traveling means for making the cutting tool travel relative to a workpiece. The rotating means and the traveling means rotates the outer peripheral surface of the cutting tool and makes the cutting tool travel, having the outer peripheral surface function as the rake surface, so as to perform cutting machining.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 4, 2017
    Applicant: JTEKT CORPORATION
    Inventors: Takayuki AZUMA, Yoshihiko YAMADA, Kenji HAMADA, Masahiro KIJI, Hiroshi WATANABE
  • Patent number: 9640610
    Abstract: An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 2, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Naruhisa Miura
  • Patent number: 9599979
    Abstract: The present invention discloses a machining error calculation apparatus for calculating the machining error more precisely through analysis.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: March 21, 2017
    Assignee: JTEKT CORPORATION
    Inventor: Kenji Hamada
  • Publication number: 20170015880
    Abstract: An adhesive film, an optical member including the same, and an optical display including the same are disclosed. The adhesive film has a folding evaluation parameter 1 of about 900% to about 1,300% at 25° C., as calculated by Equation 1 and a folding evaluation parameter 2 of about 40% to about 95% at 60° C., as calculated by Equation 2, and includes a hydroxyl group-containing (meth)acrylic copolymer.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 19, 2017
    Inventors: Ji Ho Kim, Byeong Do Kwak, Il Jin Kim, Kenji Hamada, Yong Tae Kim, Hyung Rang Moon, Woo Jin Lee, Ik Hwan Cho, In Chul Hwang
  • Patent number: 9536942
    Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: January 3, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Kenji Hamada, Kohei Ebihara, Akihiko Furukawa, Yuji Murakami
  • Publication number: 20160336390
    Abstract: An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.
    Type: Application
    Filed: February 6, 2015
    Publication date: November 17, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenji HAMADA, Naruhisa MIURA
  • Publication number: 20160276849
    Abstract: In a balance correction circuit including a plurality of converter type balance correction units that control a supply of a current to a plurality of power storage cells by complementarily on/off controlling two switching elements and hereby allowing to exchange power between or among power storage cells via an inductor to equalize the voltages of the power storage cells, a common timing signal used to generate a control signal of a switching element is supplied to each of the above balance correction units. For example, the balance correction circuit generates a timing signal to supply to a first balance correction unit based on a variation in a voltage applied to the capacitive element charged by a voltage difference created between a control signal generated by the second balance correction unit and a second power storage cell cathode of the balance correction unit.
    Type: Application
    Filed: October 16, 2014
    Publication date: September 22, 2016
    Applicant: FDK CORPORATION
    Inventor: Kenji HAMADA
  • Publication number: 20160247894
    Abstract: A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: August 25, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji HAMADA, Masayuki IMAIZUMI
  • Patent number: 9421657
    Abstract: The present invention discloses a machining control apparatus capable of decreasing a machining error, comprising: a rotation velocity decision process part for deciding a rotation velocity of the rotation tool in such a way that an amplitude of vibration of the rotation tool is decreased, based on a vibration state of the rotation tool and a vibration phase of the rotation tool when the rotation tool receives the cutting resistance force, in the case that the rotation tool vibrates due to the interrupted cutting resistance force generated in the rotation tool during the interrupted cutting; and a rotation velocity control part for controlling the rotation velocity(S) of the rotation tool based on the rotation velocity decided.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 23, 2016
    Assignee: JTEKT Corporation
    Inventors: Kenji Hamada, Shinji Murakami, Yoshihiko Yamada
  • Patent number: 9414807
    Abstract: An ultrasound diagnosis system, a medical image display apparatus and displaying method that simultaneously acquires virtual endoscopy image data and multi-planar-reconstruction (MPR) image data of a diagnosing target region based on the volume data acquired from an object. Virtual endoscopy image data is generated by setting up a viewing point and a viewing direction on a volume data acquired from the object. A marker is provided on a target region of a lumen organ shown in the virtual endoscopy image data for setting up an observing direction. A reference line started from the volume data is set up along an observing direction. By comparing a voxel value of the volume data that is crossing to the reference line with a prescribed threshold value, a reference point where a surface of the diagnosing target region crosses the reference line is set up to the volume data.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: August 16, 2016
    Assignee: Toshiba Medical Systems Corporation
    Inventors: Kenji Hamada, Yoshitaka Mine, Itsuki Kuga, Eiichi Shiki
  • Publication number: 20160087031
    Abstract: A semiconductor device including a terminal region that can suppress a resist collapse in manufacturing and effectively relieve a concentration of electric fields and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor element formed in a semiconductor substrate made of a silicon carbide semiconductor of a first conductivity type and a plurality of ring-shaped regions of a second conductivity type formed in the semiconductor substrate while surrounding the semiconductor element in plan view. At least one of the plurality of ring-shaped regions includes one or more separation regions of the first conductivity type that cause areas of the first conductivity type on an inner side and an outer side of one of the ring-shaped regions to communicate with each other in plan view.
    Type: Application
    Filed: May 2, 2014
    Publication date: March 24, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kohei EBIHARA, Naruhisa MIURA, Kenji HAMADA, Koji OKUNO
  • Patent number: 9282324
    Abstract: A medical image diagnosis apparatus according to an embodiment includes a rendering processing unit, a display unit, and a control unit. The rendering processing unit is configured to perform rendering processing from a plurality of viewpoints on volume data that is three-dimensional medical image data to create a parallax image group composed of a predefined number of parallax images. The display unit is configured to display the parallax image group to display a stereoscopic image recognized stereoscopically by an observer. The control unit configured to perform control so that a composite image group of the parallax image group and an information image is displayed on the display unit in such a manner that a first region displaying the parallax image group on the display unit is distinguishable from a second region displaying the information image indicating information other than the parallax image group on the display unit.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: March 8, 2016
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventor: Kenji Hamada