Patents by Inventor Kenji Sakurada
Kenji Sakurada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908526Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.Type: GrantFiled: January 31, 2022Date of Patent: February 20, 2024Assignee: Kioxia CorporationInventors: Naoto Kumano, Kenji Sakurada
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Patent number: 11869601Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.Type: GrantFiled: November 7, 2022Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Kenji Sakurada, Naomi Takeda, Masanobu Shirakawa, Marie Takada
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Publication number: 20230326526Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.Type: ApplicationFiled: March 23, 2022Publication date: October 12, 2023Applicant: Kioxia CorporationInventors: Avi Steiner, Kenji Sakurada, Eyal Nitzan, Yasuhiko Kurosawa
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Patent number: 11768732Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.Type: GrantFiled: November 19, 2021Date of Patent: September 26, 2023Assignee: KIOXIA CORPORATIONInventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
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Publication number: 20230298685Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.Type: ApplicationFiled: August 26, 2022Publication date: September 21, 2023Inventors: Motoki SHIMIZU, Kenji SAKURADA, Naoto KUMANO
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Publication number: 20230088099Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.Type: ApplicationFiled: November 7, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Kenji SAKURADA, Naomi TAKEDA, Masanobu SHIRAKAWA, Marie TAKADA
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Publication number: 20230045340Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.Type: ApplicationFiled: January 31, 2022Publication date: February 9, 2023Inventors: Naoto KUMANO, Kenji SAKURADA
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Patent number: 11545223Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.Type: GrantFiled: December 10, 2020Date of Patent: January 3, 2023Assignee: Kioxia CorporationInventors: Kenji Sakurada, Naomi Takeda, Masanobu Shirakawa, Marie Takada
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Publication number: 20220075686Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yuta KUMANO, Hironori UCHIKAWA, Kosuke MORINAGA, Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE
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Patent number: 11210163Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.Type: GrantFiled: November 12, 2019Date of Patent: December 28, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
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Patent number: 11211950Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.Type: GrantFiled: September 14, 2020Date of Patent: December 28, 2021Assignee: Kioxia CorporationInventors: Kuminori Hyodo, Kenji Sakurada, Yasuhiko Kurosawa, Takashi Nakagawa
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Publication number: 20210375372Abstract: A memory system in an embodiment includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.Type: ApplicationFiled: December 10, 2020Publication date: December 2, 2021Applicant: Kioxia CorporationInventors: Kenji SAKURADA, Naomi TAKEDA, Masanobu SHIRAKAWA, Marie TAKADA
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Publication number: 20210211142Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.Type: ApplicationFiled: September 14, 2020Publication date: July 8, 2021Applicant: Kioxia CorporationInventors: Kuminori HYODO, Kenji SAKURADA, Yasuhiko KUROSAWA, Takashi NAKAGAWA
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Patent number: 10726911Abstract: A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.Type: GrantFiled: September 4, 2018Date of Patent: July 28, 2020Assignee: Toshiba Memory CorporationInventors: Kuminori Hyodo, Kenji Sakurada, Masanobu Shirakawa, Hideki Yamada
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Publication number: 20200081770Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Applicant: Toshiba Memory CorporationInventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
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Patent number: 10566049Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a first latch circuit; and a second latch circuit. The first latch circuit and the second latch circuit are associated with the first memory cell. When the semiconductor memory device receives, from an external device, a first address designating one of the first latch circuit and the second latch circuit and a read command for data of the first memory cell, data is read from the first memory cell and the read data is held in the one of the first latch circuit and the second latch circuit corresponding to the first address.Type: GrantFiled: February 14, 2018Date of Patent: February 18, 2020Assignee: Toshiba Memory CorporationInventors: Kenji Sakurada, Masanobu Shirakawa
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Publication number: 20190295634Abstract: A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.Type: ApplicationFiled: September 4, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Kuminori HYODO, Kenji SAKURADA, Masanobu SHIRAKAWA, Hideki YAMADA
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Publication number: 20190220348Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value read from the non-volatile memory to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.Type: ApplicationFiled: September 11, 2018Publication date: July 18, 2019Applicant: Toshiba Memory CorporationInventors: Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE, Hironori UCHIKAWA
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Patent number: 10320429Abstract: According to the embodiment, a memory controller includes a memory interface which performs a first reading using a read voltage including a hard decision voltage and a second reading using a plurality of read voltages within a predetermined voltage range, a shift value calculation unit which calculates an update value of the hard decision voltage based on the reading result by the second reading, a storage unit which stores the update value, a decoding unit which performs decoding based on likelihood information according to the reading result, and a controller which makes the memory controller perform the first reading, makes the decoding unit perform the decoding by using the likelihood information using a reading result by the second reading when the decoding has been failed, and makes the memory controller perform the first reading by using the update value when the corresponding update value is stored in the storage unit.Type: GrantFiled: July 2, 2015Date of Patent: June 11, 2019Assignee: Toshiba Memory CorporationInventor: Kenji Sakurada
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Patent number: 10297338Abstract: A memory system includes: a semiconductor memory device; and a controller capable of issuing a first read instruction and a second read instruction different from the first read instruction. When receiving the first read instruction, the semiconductor memory device reads first data and second data from a memory cell array, holds the first data and the second data in the latch circuit, and outputs the first data to the controller. When receiving the second read instruction, the semiconductor memory device outputs third data based on the second data held by the latch circuit to the controller. The controller performs soft decision processing using the third data.Type: GrantFiled: March 10, 2017Date of Patent: May 21, 2019Assignee: Toshiba Memory CorporationInventors: Masanobu Shirakawa, Kenji Sakurada, Hitoshi Shiga