Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a first latch circuit; and a second latch circuit. The first latch circuit and the second latch circuit are associated with the first memory cell. When the semiconductor memory device receives, from an external device, a first address designating one of the first latch circuit and the second latch circuit and a read command for data of the first memory cell, data is read from the first memory cell and the read data is held in the one of the first latch circuit and the second latch circuit corresponding to the first address.

Abstract: According to one embodiment, a memory system includes a decoder configured to correct an error of the data stored in a memory based on result of the first read and the second read, and output a first signal of a first value indicating corrected data and a second signal of a second value indicating corrected data; a generator configured to count the first and second signals for first data items based on the result of the first and second read for generating count numbers of the first and second signals for each of the first data items; and a controller configured to compare a magnitude relation of the count numbers in order of read levels, determine the first data item when the magnitude relation changes.

Abstract: A memory system and method is provided. The memory system includes a non-volatile memory, a memory interface, and a code processor. The code processor generates a likelihood value for a first read bit, which is read from a first memory cell, from among read bits contained in a codeword read by the memory interface from the non-volatile memory. For example, the likelihood value can be based on the value of the first read bit and on the value of a second read bit read from a second memory cell adjacent to the first memory cell so as to decode the codeword using the generated likelihood value.

Abstract: According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE, UPPER, and HIGHER pages from a NAND memory 100 that includes QLCs each being capable of retaining a 4-bit value. An ECC circuit 260 of a memory controller 200 decodes the acquired HB information and SB1 to SB4 information on the four pages.

Abstract: A memory system includes: a semiconductor memory device; and a controller capable of issuing a first read instruction and a second read instruction different from the first read instruction. When receiving the first read instruction, the semiconductor memory device reads first data and second data from a memory cell array, holds the first data and the second data in the latch circuit, and outputs the first data to the controller. When receiving the second read instruction, the semiconductor memory device outputs third data based on the second data held by the latch circuit to the controller. The controller performs soft decision processing using the third data.

Abstract: According to one embodiment, a memory system includes a decoder configured to correct an error of the data stored in a memory based on result of the first read and the second read, and output a first signal of a first value indicating corrected data and a second signal of a second value indicating corrected data; a generator configured to count the first and second signals for first data items based on the result of the first and second read for generating count numbers of the first and second signals for each of the first data items; and a controller configured to compare a magnitude relation of the count numbers in order of read levels, determine the first data item when the magnitude relation changes.

Abstract: According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ECC frames into likelihood information based on a set table, generates decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful. The calculation section generates calculation data based on an ECC frame of calculation target among the decoded ECC frames and its ECC frame before decoded. The table creation section sets the new table to the decoder based on the calculation data. The control section controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful.

Abstract: A memory system and method is provided. The memory system includes a non-volatile memory, a memory interface, and a code processor. The code processor generates a likelihood value for a first read bit, which is read from a first memory cell, from among read bits contained in a codeword read by the memory interface from the non-volatile memory. For example, the likelihood value can be based on the value of the first read bit and on the value of a second read bit read from a second memory cell adjacent to the first memory cell so as to decode the codeword using the generated likelihood value.

Abstract: According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE, UPPER, and HIGHER pages from a NAND memory 100 that includes QLCs each being capable of retaining a 4-bit value. An ECC circuit 260 of a memory controller 200 decodes the acquired HB information and SB1 to SB4 information on the four pages.

Abstract: According to one embodiment, a memory controller controlling a nonvolatile memory which stores a code word includes a read control unit which controls reading from the nonvolatile memory and a decoding unit which obtains likelihood information of each memory cells based on a reading result from the nonvolatile memory and decodes the code word by using the likelihood information, wherein the decoding unit obtains the likelihood information of a first memory cell based on the reading result of the first memory cell and the reading results of second memory cells which are one or more of the memory cells adjacent to the first memory cell.

Abstract: According to the embodiment, a memory controller includes a memory interface which performs a first reading using a read voltage including a hard decision voltage and a second reading using a plurality of read voltages within a predetermined voltage range, a shift value calculation unit which calculates an update value of the hard decision voltage based on the reading result by the second reading, a storage unit which stores the update value, a decoding unit which performs decoding based on likelihood information according to the reading result, and a controller which makes the memory controller perform the first reading, makes the decoding unit perform the decoding by using the likelihood information using a reading result by the second reading when the decoding has been failed, and makes the memory controller perform the first reading by using the update value when the corresponding update value is stored in the storage unit.

Abstract: According to one embodiment, a memory controller includes a decoding unit. The decoding unit calculates a syndrome weight in an LDPC code using a codeword read out from a non-volatile memory. The memory controller instructs the non-volatile memory to perform readout using first and second read-out voltages, and determines the first read-out voltage as the optimal read-out voltage in the case where a first syndrome weight based on a read-out result at the first read-out voltage is equal to or less than a second syndrome weight based on a read-out result at the second read-out voltage.

Abstract: According to one embodiment, a memory controller controlling a nonvolatile memory which stores a code word includes a read control unit which controls reading from the nonvolatile memory and a decoding unit which obtains likelihood information of each memory cells based on a reading result from the nonvolatile memory and decodes the code word by using the likelihood information, wherein the decoding unit obtains the likelihood information of a first memory cell based on the reading result of the first memory cell and the reading results of second memory cells which are one or more of the memory cells adjacent to the first memory cell.

Abstract: According to one embodiment, a controller includes a generator and a creator. The generator generates a channel matrix by counting a number of times a combination of a correct bit value and a read level appears for each bit forming a decoded first frame, based on readout data indicating a read level of each of a plurality of bits forming a frame and the decoded frame. The creator creates a table by statistically calculating a likelihood of a correct bit value of each read level based on the channel matrix.

Abstract: According to one embodiment, a memory controller includes a decoding unit. The decoding unit calculates a syndrome weight in an LDPC code using a codeword read out from a non-volatile memory. The memory controller instructs the non-volatile memory to perform readout using first and second read-out voltages, and determines the first read-out voltage as the optimal read-out voltage in the case where a first syndrome weight based on a read-out result at the first read-out voltage is equal to or less than a second syndrome weight based on a read-out result at the second read-out voltage.

Abstract: According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ECC frames into likelihood information based on a set table, generates decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful. The calculation section generates calculation data based on an ECC frame of calculation target among the decoded ECC frames and its ECC frame before decoded. The table creation section sets the new table to the decoder based on the calculation data. The control section controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful.

Abstract: According to one embodiment, a controller includes a generator and a creator. The generator generates a channel matrix by counting a number of times a combination of a correct bit value and a read level appears for each bit forming a decoded first frame, based on readout data indicating a read level of each of a plurality of bits forming a frame and the decoded frame. The creator creates a table by statistically calculating a likelihood of a correct bit value of each read level based on the channel matrix.

Abstract: A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.

Abstract: A memory card includes: a plurality of memory cells; a CPU core; and an ECC unit configured to perform soft decision decoding. If decoding based on an LLR acquired from a first LLR table fails, the memory card measures a threshold voltage distribution centered on a first HB read voltage with a highest voltage. If a first shift value as a difference between a least frequent voltage of the threshold voltage distribution and the first HB read voltage is “negative”, the memory card performs decoding based on an LLR acquired from the second LLR table. If the first shift value is “positive”, the memory card performs decoding based on an LLR acquired from a third LLR table.

Abstract: A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.