Abstract: The present invention effectively cancels echo, near-end crosstalk and far-end crosstalk. A FEXT canceller is placed at the transmitter rather than at the receiver according to an aspect of the invention. In some embodiment, a FEXT canceller can be placed at the receiver only or the combination of both ends. The FEXT canceller is continuously adapted with information sent back from a remote receiver and with data from a neighbor transmitter that causes the crosstalk at the remote receiver. This allows the FEXT canceller to quickly adapt to a change in crosstalk function or conditions with the surrounding environment, for example, aging, temperature, humidity, physical pressure, etc. In some embodiments, an adaptation control signal is sent back from the receiver to the transmitter by using an overhead bit in the frame format. In some embodiments, part of the FEXT canceller is built-in at the remote receiver.

Abstract: An adaptive electromagnetic interference (EMI) detection and reduction device for multi-port applications is provided. The invention includes at least two physical devices (PHY), where the PHYs transmit data along wire pairs to a register jack (RJ). The transmissions create EMI along the wire pairs, where the transmissions have constructively interfering resonant frequencies having phases and amplitudes. An antenna is disposed proximal to each RJ, where the antennae detect each frequency. A resonating network determines a peak amplitude of each frequency, an envelope detector amplifies each peak amplitude from the resonating network. A discretization circuit converts the amplified peak to discrete amplitude values, where the discretization circuit transmits the discrete amplitude values to a controller.

Abstract: A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.

Abstract: A 10GBASE-T clocking method that limits EMI and increases SNR, while reducing power and conserving chip space is provided. The method includes simultaneous clocking of transmitters in an analog front end of a 10 gigabit Ethernet. The method includes providing at least two channels to a 10GBase-T analog front end, where the channel has at least a transmitter port and a receiver port, and providing at least two phase interpreters to the analog front end, where each phase interpreter is dedicated to one receiver port. A central clock generator is disposed to distribute a transmit clock to the phase interpreters and to the transmitter ports, where the transmit clock is further provided to the receiver ports from the phase interpreters. Any clock delay between the clock generator and each channel is balanced and clock phases between the channels are matched.

Abstract: By constructing the stages of a pipelined analog to digital converter (ADC) such that they are in close proximity while sharing a voltage reference, bias, and power supply, the linearity of the ADC's will match since the relatively large devices that now dictate the ADC linearity are in close proximity to one another. Supply and reference IR drops are also matched reducing gain and linearity mismatch. Based on this, it is possible to construct a shared multi-channel ADC with exceptionally good matching of gain, phase, and linearity without additional hardware to match the channels.

Abstract: An operational amplifier circuit that provides negative feedback and high gain is described. Specifically, the circuit comprises a first gain stage, a second gain stage, a feedback circuit, and a biasing circuit.

Abstract: High speed data transmission schemes often use differential lines to reduce the effect of noise on the data signal. Unfortunately, the signal propagation on the positive and negative lines may be different, which leads to a signal skew problem. This document describes a novel way of compensating for differential line skew in data transmission lines.

Abstract: A hybrid system with adjustable on-chip components and a method calibrating the same invariably maximizes hybrid performance despite of on- and off-chip component mismatches and imperfections. The hybrid system has a main DAC, a replica DAC, and three or four resistors. Both DACs are directly connected to digital data. An adjustable resistor is connected to the main DAC and is calibrated such that output impedance is automatically adjusted to match an off-chip load impedance Z. A replica DAC current K is calibrated for optimum DC matching in presence of Z. An adjustable capacitor C2 is calibrated for slope-matching (bandwidth matching). If Z changes, the calibration procedure should be repeated for optimal performance. These three calibration mechanisms can be utilized individually or in combination. The present invention is compatible with both analog and digital echo-cancellers.

Abstract: A biasing technique between a first circuit stage and a second circuit stage is described. Specifically, the technique comprises using a combination of thin and thick oxide transistors.

Abstract: An operational amplifier circuit that provides negative feedback and high gain is described. Specifically, the circuit comprises a first gain stage, a second gain stage, a feedback circuit, and a biasing circuit.

Abstract: An adaptive bias module architecture and related methods is presented. According to one embodiment, for example, a method is presented comprising detecting a power level associated with data received by a transmit driver for transmission into an inductive load without analyzing the data content, and adapting a bias level applied to the transmit driver to facilitate transmission of the received data based, at least in part, on the detected power level.

Abstract: An adaptive bias module architecture and related methods is presented. According to one embodiment, for example, a method is presented comprising detecting a power level associated with data received by a transmit driver for transmission into an inductive load without analyzing the data content, and adapting a bias level applied to the transmit driver to facilitate transmission of the received data based, at least in part, on the detected power level.