Abstract: A photosensitive resin composition for flexographic printing having excellent resistance to an ink comprising an organic solvent and an emulsion ink used in flexographic printing, for example, a UV-curable ink or an ink using a vegetable oil or light naphtha and having excellent suitability for printing applications such as image reproducibility and print durability. The photosensitive resin composition for flexographic printing includes, at least, (a) one or more thermoplastic elastomers, (b) an acrylic-terminated liquid polybutadiene containing 1,2-bonds in an amount of 80% or more, (c) a photopolymerizable unsaturated monomer having at least one or more ethylenically unsaturated groups, and (d) a photopolymerization initiator.

Abstract: Each unit cell includes: a drift layer 3 made of an n-type wide bandgap semiconductor formed on a substrate 2 made of an n-type wide bandgap semiconductor; a p-type well 4a provided in the driwhoseft layer 3; a first n-type impurity region 5 provided in the well 4a; a surface channel layer 7b formed at least on a surface of the well so as to connect together the first n-type impurity region 5 and the drift layer 3; a second n-type impurity region 7a provided in a surface region of the well which is under the surface channel layer and which spans the first n-type impurity region 5 and the drift layer 3, the second n-type impurity region 7a having an impurity concentration generally equal to or greater than an impurity concentration of the well 4a; and a third n-type impurity region formed in a surface region of the drift layer 3 adjacent to the second n-type impurity region 7a.

Abstract: In a semiconductor element (20) including a field effect transistor (90), a schottky electrode (9a) and a plurality of bonding pads (12S, 12G), at least one of the plurality of bonding pads (12S, 12G) is disposed so as to be located above the schottky electrode (9a).

Abstract: The semiconductor device includes: a substrate 2 and a drift layer 3a, which are made of a wide-bandgap semiconductor; a p-type well 4a and a first n-type doped region 5, which are defined in the drift layer; a source electrode 5, which is electrically connected to the first n-type doped region 5; a second n-type doped region 30 arranged between its own well 4a and an adjacent unit cell's well 4a; a gate insulating film 7b, which covers at least partially the first and second n-type doped regions and the well 4a; a gate electrode 8 arranged on the gate insulating film; and a third n-type doped region 31, which is arranged adjacent to the second n-type doped region so as to cover one of the vertices of the unit cell and which has a dopant concentration that is higher than the drift layer and lower than the second n-type doped region.

Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.

Abstract: A semiconductor element (20) of the present invention includes a plurality of field effect transistors (90) and a schottky electrode (9a), and the schottky electrode (9a) is formed along an outer periphery of a region where the plurality of field effect transistors (90) are formed.

Abstract: A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.

Abstract: A semiconductor element (20) of the present invention includes a plurality of field effect transistors (90) and a schottky electrode (9a), and the schottky electrode (9a) is formed along an outer periphery of a region where the plurality of field effect transistors (90) are formed.

Abstract: In a semiconductor element (20) including a field effect transistor (90), a schottky electrode (9a) and a plurality of bonding pads (12S, 12G), at least one of the plurality of bonding pads (12S, 12G) is disposed so as to be located above the schottky electrode (9a).

Abstract: A gate insulating film which is an oxide layer mainly made of SiO2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100° C. and lower than 1250° C., whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.

Abstract: A field-effect transistor power device includes a source electrode, a drain electrode, a wide gap semiconductor including a channel region and a drift region, the channel region and the drift region forming a series current path between the source electrode and the drain electrode, a gate insulating film that covers the channel region, and a gate electrode formed on the gate insulating film. In the series current path which is electrically conducting when the field-effect transistor power device is in an ON state, any region other than the channel region has an ON resistance exhibiting a positive temperature dependence, and the channel region has an ON resistance exhibiting a negative temperature dependence. A ratio ?Ron/Ron(?30° C.) is 50% or less.

Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple ?-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and ?-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

Abstract: A power device having a transistor structure is formed by using a wide band gap semiconductor. A current path 20 of the power device includes: a JFET (junction) region 2, a drift region 3, and a substrate 4, which have ON resistances exhibiting a positive temperature dependence; and a channel region 1, which has an ON resistance exhibiting a negative temperature dependence. A temperature-induced change in the ON resistance of the entire power device is derived by allowing a temperature-induced change ?Rp in the ON resistance in the JFET (junction) region 2, the drift region 3, and the substrate 4, which have ON resistances exhibiting a positive temperature dependence, and a temperature-induced change ?Rn in the ON resistance in the channel region 1, which has an ON resistance exhibiting a negative temperature dependence, to cancel out each other. With respect to an ON resistance of the entire power device at ?30° C.

Abstract: A semiconductor device according to this invention includes: two level shift switches (28A and 28B) each having first and second electrodes, a control electrode, a signal output electrode, and a first semiconductor region forming a transistor device section (28a,28b) which intervenes between the first electrode and the signal output electrode and is brought into or out of conduction according to a signal inputted to the control electrode and a resistor device section (Ra,Rb) which intervenes between the signal output electrode and the second electrode, the first semiconductor region comprising a wide bandgap semiconductor; and a diode (23) having a cathode-side electrode, an anode-side electrode, and a second semiconductor region comprising a wide bandgap semiconductor.

Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

Abstract: In a position display system, position-related information related with real positions of respective information processing terminals are obtained; the position-related information is transmitted to a server; real positions of the respective information processing terminals based on the position-related information are stored; past real positions satisfying the condition of being before the present time by a prescribed period of time and more are generated as display positions for the respective information processing terminals; the display positions of the respective information processing terminals are obtained from the server; and the display positions of said a plurality of information processing terminals are displayed on the screens of the respective information processing terminals. Real positions at which respective users have been actually present but which are not the present real positions of the users and are at times before a prescribed period of time and more are displayed.