Patents by Inventor Kenya Yamashitas

Kenya Yamashitas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040051104
    Abstract: A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a &dgr; doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration &dgr; doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.
    Type: Application
    Filed: July 14, 2003
    Publication date: March 18, 2004
    Inventors: Kenya Yamashita, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Masao Uchida, Ryoko Miyanaga
  • Patent number: 6600203
    Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: July 29, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kunimasa Takahashi, Toshiya Yokogawa, Makoto Kitabatake, Masao Uchida, Osamu Kusumoto, Kenya Yamashita
  • Patent number: 6580125
    Abstract: A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: June 17, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
  • Publication number: 20030080384
    Abstract: A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat &dgr;-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 1, 2003
    Applicant: Matsushita Electric Industrial Co.., Ltd.
    Inventors: Kunimasa Takahashi, Masao Uchida, Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Kenya Yamashita, Ryoko Miyanaga
  • Publication number: 20030020136
    Abstract: A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.
    Type: Application
    Filed: August 15, 2002
    Publication date: January 30, 2003
    Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
  • Publication number: 20020179909
    Abstract: A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 5, 2002
    Inventors: Masao Uchida, Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Kunimasa Takahashi, Ryoko Miyanaga, Kenya Yamashita
  • Publication number: 20020158251
    Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 31, 2002
    Inventors: Kunimasa Takahashi, Toshiya Yokogawa, Makoto Kitabatake, Masao Uchida, Osamu Kusumoto, Kenya Yamashita