Patents by Inventor Kenzo Ishida

Kenzo Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7724990
    Abstract: A technique for monitoring optical power in a fiber array unit having a plurality of optical transmission waveguides terminating at an edge thereof for carrying optical signals to and/or from a PLC. A tapping filter is placed within a slit formed in the substrate and interrupting the transmission channels, thereby tapping at least some of the optical power from the channels and directing the tapped optical power toward respective photodetector channels for detection, while allowing other optical power to continue transmission in the at least one channel of the fiber array unit.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: May 25, 2010
    Assignee: AiDi Corporation
    Inventor: Kenzo Ishida
  • Publication number: 20090016716
    Abstract: A technique for monitoring optical power in a fiber array unit having a plurality of optical transmission waveguides terminating at an edge thereof for carrying optical signals to and/or from a PLC. A tapping filter is placed within a slit formed in the substrate and interrupting the transmission channels, thereby tapping at least some of the optical power from the channels and directing the tapped optical power toward respective photodetector channels for detection, while allowing other optical power to continue transmission in the at least one channel of the fiber array unit.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 15, 2009
    Applicant: AIDI CORPORATION
    Inventor: Kenzo ISHIDA
  • Patent number: 7330620
    Abstract: A funnel-type planar lightwave circuit (PLC) optical splitter having an input optical waveguide, a slab waveguide receiving the input optical signal from the input optical waveguide, and output waveguides projecting from the slab region. The region connecting the slab waveguide to the output waveguides is characterized by a segmented taper structure. In another additional, or alternative aspect of the present invention, a cladding mode absorption region runs along either or both sides of the input optical waveguide. A funnel-type splitter with both a cladding mode absorption region and a segmented taper structure provides a “super” low loss splitter design, when considering both insertion loss and polarization dependent loss. Advantageously, the disclosed funnel-type PLC splitter does not require a quartz substrate due to its very low PDL, and a silicon substrate can be used. Silicon substrates are known to be lower cost, with a higher resistance to fracture.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 12, 2008
    Assignee: Aidi Corporation
    Inventors: Kenzo Ishida, Alan Tafapolsky, Takaharu Fujiyama
  • Publication number: 20070196050
    Abstract: A funnel-type planar lightwave circuit (PLC) optical splitter having an input optical waveguide, a slab waveguide receiving the input optical signal from the input optical waveguide, and output waveguides projecting from the slab region. The region connecting the slab waveguide to the output waveguides is characterized by a segmented taper structure. In another additional, or alternative aspect of the present invention, a cladding mode absorption region runs along either or both sides of the input optical waveguide. A funnel-type splitter with both a cladding mode absorption region and a segmented taper structure provides a “super” low loss splitter design, when considering both insertion loss and polarization dependent loss. Advantageously, the disclosed funnel-type PLC splitter does not require a quartz substrate due to its very low PDL, and a silicon substrate can be used. Silicon substrates are known to be lower cost, with a higher resistance to fracture.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 23, 2007
    Applicant: AIDI CORPORATION
    Inventors: Kenzo ISHIDA, Alan TAFAPOLSKY, Takaharu FUJIYAMA
  • Patent number: 7171743
    Abstract: An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: February 6, 2007
    Assignee: Intel Corporation
    Inventor: Kenzo Ishida
  • Publication number: 20040209542
    Abstract: An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.
    Type: Application
    Filed: May 7, 2004
    Publication date: October 21, 2004
    Inventor: Kenzo Ishida
  • Patent number: 6798137
    Abstract: An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: September 28, 2004
    Assignee: Intel Corporation
    Inventor: Kenzo Ishida
  • Patent number: 6785148
    Abstract: A socket for mounting a processor and/or a board has a substrate with a built in socket. The socket has conductive, elastically deformable terminals. The socket may be mounted to a processor and a board without using conventional surface mount technology, instead providing a mechanical contact mechanism between the socket and the board or processor. An adhesive layer may also be used to connect the socket to a processor and/or a board.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventors: Kenzo Ishida, Shuji Inoue, Kinya Ichikawa, Kenji Takahashi
  • Publication number: 20040100187
    Abstract: An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 27, 2004
    Inventor: Kenzo Ishida
  • Patent number: 6697553
    Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: February 24, 2004
    Assignee: JDS Uniphase Corporation
    Inventors: Jyoti Kiron Bhardwaj, Robert James Brainard, David J. Chapman, Douglas E. Crafts, Zi-Wen Dong, David Dougherty, Erik W. Egan, James F. Farrell, Mark B. Farrelly, Niranjan Gopinathan, Kenzo Ishida, David K. Nakamoto, Thomas Thuan Nguyen, Suresh Ramalingam, Steven M. Swain, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
  • Patent number: 6665475
    Abstract: A groove assembly for holding at least one fiber optic. The assembly includes a base, a cover and a small carrier disposed between the base and the cover. The carrier has at least one groove. At least one fiber optic is disposed in this groove and terminates at an edge surface of the carrier. The base and cover have respective edge surfaces serving as attachment surfaces for attachment of the assembly to a planar lightwave circuit (PLC). The PLC has at least one waveguide terminating at an edge, to which the fiber requires alignment. The base and/or cover are preferably formed from a material enabling attachment to the PLC, e.g., transparent to energy used for curing an adhesive. The carrier is formed from material enabling a substantially more precise formation of the grooves, e.g., silicon.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: December 16, 2003
    Assignee: JDS Uniphase Corporation
    Inventor: Kenzo Ishida
  • Patent number: 6664511
    Abstract: A package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package, which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar light-wave circuit (PLC), e.g. an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: December 16, 2003
    Assignee: JDS Uniphase Corporation
    Inventors: Douglas E. Crafts, James F. Farrell, Mark B. Farrelly, Suresh Ramalingam, Kenzo Ishida
  • Publication number: 20030156789
    Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).
    Type: Application
    Filed: February 15, 2002
    Publication date: August 21, 2003
    Inventors: Jyoti Kiron Bhardwaj, Robert James Brainard, David J. Chapman, Douglas E. Crafts, Zi-Wen Dong, David Dougherty, Erik W. Egan, James F. Farrell, Mark B. Farrelly, Niranjan Gopinathan, Kenzo Ishida, David K. Nakamoto, Thomas Thuan Nguyen, Suresh Ramalingam, Steven M. Swain, Sanjay M. Thekdi, Anantharaman Vaidyanathan, Hiroaki Yamada, Yingchao Yan
  • Patent number: 6606425
    Abstract: An optical component package, in which a transfer molded layer of material (e.g., syntactic foam in one embodiment) is formed at least partially around, or entirely around, the optical component to provide structural and thermal insulation around the component. The optical component may be a planar lightwave circuit (PLC), with a protective passivation layer formed between the PLC and the layer of syntactic foam, to de-couple stresses and thermal transfer between the PLC and the layer of syntactic foam. Strengthening caps, fiber assemblies, and a heater may be provided with the PLC assembly, around which the layer of syntactic foam can also be formed. The protective passivation layer can also be formed between these structures and the syntactic foam; in one embodiment between at least two strengthening caps formed on opposing edges of the PLC. The disclosed package provides numerous structural, thermal and size benefits.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: August 12, 2003
    Assignee: JDS Uniphase Corporation
    Inventors: Douglas E. Crafts, Kenzo Ishida, David J. Chapman, Duane Cook, James F. Farrell, Suresh Ramalingam, Steven M. Swain
  • Publication number: 20030103729
    Abstract: A groove assembly for holding at least one fiber optic. The assembly includes a base, a cover and a small carrier disposed between the base and the cover. The carrier has at least one groove. At least one fiber optic is disposed in this groove and terminates at an edge surface of the carrier. The base and cover have respective edge surfaces serving as attachment surfaces for attachment of the assembly to a planar lightwave circuit (PLC). The PLC has at least one waveguide terminating at an edge, to which the fiber requires alignment. The base and/or cover are preferably formed from a material enabling attachment to the PLC, e.g., transparent to energy used for curing an adhesive. The carrier is formed from material enabling a substantially more precise formation of the grooves, e.g., silicon.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Applicant: Scion Photonics, Inc.
    Inventor: Kenzo Ishida
  • Publication number: 20030085212
    Abstract: A package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package, which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar light-wave circuit (PLC), e.g. an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.
    Type: Application
    Filed: October 28, 2002
    Publication date: May 8, 2003
    Applicant: JDS Uniphase Corporation
    Inventors: Douglas E. Crafts, James F. Farrell, Mark B. Farrelly, Suresh Ramalingam, Kenzo Ishida
  • Patent number: 6422303
    Abstract: A heat dissipation device comprising a thermally conductive, hollow housing having a fan and an active anti-noise module disposed within the hollow housing. The hollow housing may include a plurality of fins disposed therein to increase the surface area for convective heat transfer. The heat dissipation device further may further include heat pipes for the transportation and dispersion of heat to and about an external surface of the hollow housing.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: July 23, 2002
    Assignee: Intel Corporation
    Inventors: Kenzo Ishida, Shinya Endo, Daryl J. Nelson
  • Publication number: 20020089836
    Abstract: The present invention provides a method of attaching an integrated circuit die to a substrate. The method includes applying solder bumps to contact areas, and placing the inverted integrated circuit die in a desired location such that the solder bumps are in contact with contact areas of the integrated circuit die and the substrate. The solder bumps are heated to mount the die, such that the bumps form a connection between the substrate and the integrated circuit. The gap between the die and the substrate is underfilled by injecting a molding compound into a molding die positioned over the mounted integrated circuit die.
    Type: Application
    Filed: October 26, 1999
    Publication date: July 11, 2002
    Inventors: KENZO ISHIDA, KENJI TAKAHASHI, JIRO KUBOTA
  • Patent number: 6278185
    Abstract: A substrate which has a first conductive layer that is attached to a first dielectric layer. A second conductive layer is attached to the first dielectric layer. The second conductive layer may be a plated copper material that extends through a via opening of the dielectric and is attached to the first conductive layer. A third conductive layer is attached to the second conductive layer, including a sidewall of the third layer. A second dielectric can be attached to the third conductive layer. The third conductive layer may be a plated nickel-copper composition which improves the adhesion to subsequent layers in the substrate, particularly between the second dielectric and the sidewall of the second conductive layer.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: August 21, 2001
    Assignee: Intel Corporation
    Inventors: Venkatesan Murali, Kenzo Ishida, Brian A. Kaiser, Anant Vaidyanathan
  • Patent number: 6173576
    Abstract: A cooling unit for an integrated circuit. The cooling unit may include a peltier device that may be coupled to the integrated circuit and a plurality of fins that are thermally coupled to the peltier device. The fins may be separated by at least one channel. The cooling unit may include a fan that generates a flow of fluid through the channel.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: January 16, 2001
    Assignee: Intel Corporation
    Inventors: Kenzo Ishida, Shuji Inoue