Patents by Inventor Keun-Hwi Cho
Keun-Hwi Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990534Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.Type: GrantFiled: August 12, 2022Date of Patent: May 21, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dongwon Kim, Minyi Kim, Keun Hwi Cho
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Publication number: 20240162293Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.Type: ApplicationFiled: January 18, 2024Publication date: May 16, 2024Inventors: Jinbum Kim, DAHYE KIM, SEOKHOON KIM, JAEMUN KIM, Ilgyou Shin, Haejun YU, KYUNGIN CHOI, KIHYUN HWANG, SANGMOON LEE, SEUNG HUN LEE, KEUN HWI CHO
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Patent number: 11978805Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.Type: GrantFiled: February 17, 2023Date of Patent: May 7, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Soonmoon Jung, Daewon Ha, Sungmin Kim, Hyojin Kim, Keun Hwi Cho
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Publication number: 20240145476Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myoung-Sun LEE, Keun Hwi Cho
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Publication number: 20240136356Abstract: A semiconductor device includes a first element separation structure, a second element separation structure, and a third element separation structure sequentially disposed along a first direction and extending in a second direction intersecting the first direction; a first active pattern extending in the first direction between the first element separation structure and the second element separation structure; a second active pattern extending in the first direction between the second element separation structure and the third element separation structure and separated from the first active pattern by the second element separation structure; a first gate electrode extending in the second direction on the first active pattern; and a plurality of second gate electrodes extending in the second direction on the second active pattern, wherein a width of the first active pattern in the second direction is greater than a width of the second active pattern in the second direction.Type: ApplicationFiled: October 12, 2023Publication date: April 25, 2024Inventors: Byeol Hae EOM, Byung Ha CHOI, Keun Hwi CHO, Sung Won KIM, Yuri MASUOKA, Won Cheol JEONG
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Publication number: 20240063275Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.Type: ApplicationFiled: October 26, 2023Publication date: February 22, 2024Inventors: Sang Hoon Lee, Chang Woo Sohn, Keun Hwi Cho, Sang Won Baek
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Patent number: 11908867Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.Type: GrantFiled: January 20, 2023Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myoung-Sun Lee, Keun Hwi Cho
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Publication number: 20240038763Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.Type: ApplicationFiled: October 13, 2023Publication date: February 1, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Keun Hwi CHO, Sangdeok KWON, Dae Sin KIM, Dongwon KIM, Yonghee PARK, Hagju CHO
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Patent number: 11888028Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.Type: GrantFiled: July 12, 2022Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinbum Kim, Dahye Kim, Seokhoon Kim, Jaemun Kim, Ilgyou Shin, Haejun Yu, Kyungin Choi, Kihyun Hwang, Sangmoon Lee, Seung Hun Lee, Keun Hwi Cho
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Publication number: 20240014288Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.Type: ApplicationFiled: September 18, 2023Publication date: January 11, 2024Inventors: Guk Il AN, Keun Hwi CHO, Dae Won HA, Seung Seok HA
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Patent number: 11855165Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.Type: GrantFiled: October 31, 2022Date of Patent: December 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Keun Hwi Cho, Soonmoon Jung, Dongwon Kim, Myung Gil Kang
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Publication number: 20230411458Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.Type: ApplicationFiled: August 29, 2023Publication date: December 21, 2023Inventors: Ilgyou Shin, Minyi Kim, Myung Gil Kang, Jinbum Kim, Seung Hun Lee, Keun Hwi Cho
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Patent number: 11843000Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOI substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.Type: GrantFiled: June 2, 2021Date of Patent: December 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Beom Jin Park, Myung Gil Kang, Dong Won Kim, Keun Hwi Cho
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Patent number: 11837638Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.Type: GrantFiled: June 1, 2021Date of Patent: December 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoon Lee, Chang Woo Sohn, Keun Hwi Cho, Sang Won Baek
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Publication number: 20230387237Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: August 15, 2023Publication date: November 30, 2023Inventors: MYUNG GIL KANG, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Patent number: 11824059Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.Type: GrantFiled: July 7, 2021Date of Patent: November 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Keun Hwi Cho, Sangdeok Kwon, Dae Sin Kim, Dongwon Kim, Yonghee Park, Hagju Cho
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Patent number: 11799013Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.Type: GrantFiled: June 13, 2022Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Guk Il An, Keun Hwi Cho, Dae Won Ha, Seung Seok Ha
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Patent number: 11777001Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.Type: GrantFiled: May 12, 2022Date of Patent: October 3, 2023Inventors: Ilgyou Shin, Minyi Kim, Myung Gil Kang, Jinbum Kim, Seung Hun Lee, Keun Hwi Cho
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Patent number: 11769813Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: GrantFiled: October 14, 2022Date of Patent: September 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Publication number: 20230299139Abstract: A semiconductor device includes an active region on a substrate, source/drain patterns on the active region, channel patterns on the active region and connected to the source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other, gate electrodes, which are respectively on the channel patterns and are extended in a first direction and parallel to each other, and active contacts, which are electrically and respectively connected to the source/drain patterns. A bottom surface of a first active contact is located at a first level, and a bottom surface of a second active contact is located at a second level higher than the first level. A bottom surface of a third active contact is located at a third level higher than the second level.Type: ApplicationFiled: November 22, 2022Publication date: September 21, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Keun Hwi CHO, Myung Gil KANG, Gibum KIM, Dongwon KIM