Abstract: Provided is a semiconductor device having first and second gate electrodes. The semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode crossing the active region and extending in a second direction, and a second gate electrode extending in the second direction on the first gate electrode, wherein the first gate electrode has a first width in the first direction, and wherein the second gate electrode has a second width in the first direction, the second width being less than the first width.

Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied.

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied.

Abstract: In a method of manufacturing a semiconductor device, a plasma annealing and supplying a threshold voltage control gas onto a portion of a substrate is performed to form a fixed charge region including a fixed charge at a surface of the substrate. A MOS transistor is formed on the substrate including the fixed charge region. By the above processes, the threshold voltage of the MOS transistor may be easily controlled.

Abstract: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: A DRAM device includes a plug on a substrate, a conductive plate electrically connected to the plug and overlapping the substrate, at least one capacitor on the substrate and spaced apart from the plug, and at least one word line under the conductive plate and spaced apart from the conductive plate. The DRAM device further includes at least one first conductive pad under the conductive plate, the at least one first conductive pad being spaced apart from the conductive plate in a first state and being electrically connected to the conductive plate in a second state, the at least one first conductive pad being disposed between the plug and an adjacent word line of the at least one word line, and the at least one first conductive pad being electrically connected to a respective capacitor of the at least one capacitor.

Abstract: Provided are a multibit electro-mechanical memory device and a method of manufacturing the same. The device may include at least one bit line in a first direction on a substrate; at least one gate line and at least one lower word line in parallel by a given interval and in a second direction intersecting the first direction on the at least one bit line; at least one contact pad adjacent to the at least one gate line on the at least one bit line; and at least one cantilever electrode coupled to the at least one contact pad, configured to float with a void above and beneath the at least one cantilever electrode and configured to curve in a third direction vertical to the first and second directions.

Abstract: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.