Patents by Inventor Kevin J. Ash

Kevin J. Ash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11301394
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to select one of multiple cache eviction algorithms to use to evict a track from the cache. A first cache eviction algorithm determines tracks to evict from the cache. A second cache eviction algorithm determines tracks to evict from the cache, wherein the first and second cache eviction algorithms use different eviction schemes. At least one machine learning module is executed to produce output indicating one of the first cache eviction algorithm and the second cache eviction algorithm to use to select a track to evict from the cache. A track is evicted that is selected by one of the first and second cache eviction algorithms indicated in the output from the at least one machine learning module.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash
  • Patent number: 11288600
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache using a machine learning module. Performance attributes of system components affected by staging tracks from the storage to the cache are provided to a machine learning module. An output is received, from the machine learning module having processed the provided performance attributes, indicating a staging strategy indicating sectors of a track to stage into the cache comprising one of a plurality of staging strategies. Sectors of an accessed track that is not in the cache are staged into the cache according to the staging strategy indicated in the output.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: March 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11281593
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to indicate tracks in a shared cache accessed by a plurality of processors. A plurality of insertion points to a cache list for the shared cache having a least recently used (LRU) end and a most recently used (MRU) end identify tracks in the cache list. For each processor, of a plurality of processors, for which indication of tracks accessed by the processor is received, a determination is made of insertion points of the provided insertion points at which to indicate the tracks for which indication is received. The tracks are indicated at positions in the cache list with respect to the determined insertion points.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11281502
    Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew J. Kalos, Kevin J. Ash, Trung N. Nguyen
  • Patent number: 11281497
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine an allocation of stage and destage tasks. Storage performance information related to processing of Input/Output (I/O) requests with respect to the storage unit is provided to a machine learning module. The machine learning module receives a computed number of stage tasks and a computed number of destage tasks. A current number of stage tasks allocated to stage tracks from the storage unit to the cache is adjusted based on the computed number of stage tasks. A current number of destage tasks allocated to destage tracks from the cache to the storage unit is adjusted based on the computed number of destage tasks.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11281594
    Abstract: A method for maintaining statistics for data elements in a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method maintains updates to the statistics in an update area within the higher performance portion. The method determines whether the updates have reached a specified threshold and, in the event the updates have reached the specified threshold, flushes the updates from the update area to the ghost cache to update the statistics. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 11263097
    Abstract: Provided are a computer program product, system, and method for using a track format code in a cache control block for a track in a cache to process read and write requests to the track in the cache. A track format table associates track format codes with track format metadata. A determination is made as to whether the track format table has track format metadata matching track format metadata of a track staged into the cache. A determination is made as to whether a track format code from the track format table for the track format metadata in the track format table matches the track format metadata of the track staged. A cache control block for the track being added to the cache is generated including the determined track format code when the track format table has the matching track format metadata.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson
  • Patent number: 11243708
    Abstract: Provided are a computer program product, system, and method for providing track format information when mirroring updated tracks from a primary storage system to a secondary storage system. The primary storage system determines a track to mirror to the secondary storage system and determines whether there is track format information for the track to mirror. The track format information indicates a format and layout of data in the track, indicated in track metadata for the track. The primary storage system sends the track format information to the secondary storage system, in response to determining there is the track format information and mirrors the track to mirror to the secondary storage system. The secondary storage system uses the track format information for the track in the secondary cache when processing a read or write request to the mirrored track.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11237730
    Abstract: A method for improving cache hit ratios for selected volumes within a storage system is disclosed. In one embodiment, such a method includes monitoring I/O to multiple volumes residing on a storage system. The storage system includes a cache to store data associated with the volumes. The method determines, from the I/O, which particular volumes of the multiple volumes would benefit the most if provided favored status in the cache. The favored status provides increased residency time in the cache to the particular volumes compared to volumes not having the favored status. The method generates a list of the particular volumes and transmits the list to the storage system. The storage system, in turn, provides increased residency time to the particular volumes in accordance with their favored status. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Beth A. Peterson, Kevin J. Ash, Kyler A. Anderson
  • Patent number: 11226899
    Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node. The second cache of the second node is populated with the tracks in a first cache of the first node.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
  • Patent number: 11221954
    Abstract: A method for storing metadata in a cache comprising heterogeneous memory types is disclosed. The method stages data elements containing metadata into a lower performance portion of a cache. The cache includes the lower performance portion and a higher performance portion. In response to determining that the data elements are updated in the higher performance portion, the method records when the data elements were updated and invalidates the data elements in the lower performance portion. The method scans the lower performance portion for the data elements that are invalidated and re-stages, in the lower performance portion, the data elements that are invalidated and have not been updated in the higher performance portion in a last specified period of time. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 11, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 11222265
    Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect performance parameters for performing stages and destages in the storage controller. In response to an event, the machine learning module generates, via forward propagation, an output value that indicates whether to fill holes in a track of a cache by staging data to the cache prior to destage of the track. A margin of error is calculated based on comparing the generated output value to an expected output value, where the expected output value is generated from an indication of whether it is correct to fill holes in a track of the cache by staging data to the cache prior to destage of the track. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 11, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 11210227
    Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains, for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method removes the data element from the higher performance portion in accordance with a cache demotion algorithm. If the data element also resides in the lower performance portion and the write access count is below a first threshold, the method leaves the data element in the lower performance portion. If the data element also resides in the lower performance portion and the write access count is at or above the first threshold, the method removes the data element from the lower performance portion. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash
  • Patent number: 11200174
    Abstract: Provided are a computer program product, system, and method for considering a frequency of access to groups of tracks and density of the groups to select groups of tracks to destage. One of a plurality of densities for one of a plurality of groups of tracks is incremented in response to determining at least one of that the group is not ready to destage and that one of the tracks in the group in the cache transitions to being ready to destage. A determination is made of a group frequency indicating a frequency at which tracks in the group are modified. At least one of the density and the group frequency is used for each of the groups to determine whether to destage the group. The tracks in the group in the cache are destaged to the storage in response to determining to destage the group.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Lokesh M. Gupta
  • Patent number: 11188430
    Abstract: Provided are a computer program product, system, and method for managing read and write requests from a host to tracks in storage cached in a cache. A determination is made whether track format table support information for a track indicates that a track format table was previously determined to have or not have the track format code for track format metadata. Track format metadata for the track is rebuilt to determine whether the track format table includes a track format code for the rebuilt track format metadata when the track format table support information indicates that the track format table was previously determined to have a track format code for the track. The track format metadata is not rebuilt when the track format table support information indicates that the track format table was previously determined to not have a track format code for the track.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Susan K. Candelaria, Lokesh M. Gupta, Beth A. Peterson
  • Patent number: 11188431
    Abstract: Provided are a computer program product, system, and method for managing failover from a first processor node including a first cache to a second processor node including a second cache. Storage areas assigned to the first processor node are reassigned to the second processor node. For each track indicated in a cache list of tracks in the first cache for the reassigned storage areas, the first processor node adds a track identifier of the track and track format information indicating a layout and format of data in the track to a cache transfer list. The first processor node transfers the cache transfer list to the second processor node. The second processor node uses the track format information transferred with the cache transfer list to process read and write requests to tracks in the reassigned storage areas staged into the second cache.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11182307
    Abstract: A method for demoting data elements from a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method maintains, for the ghost cache, multiple LRU lists that designate an order in which data elements are demoted from the lower performance portion. The method utilizes the statistics to determine in which LRU lists the data elements are referenced. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash
  • Patent number: 11176052
    Abstract: A method for improving cache hit ratios for selected volumes within a storage system is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a “non-favored” LRU list that contains entries associated with non-favored storage elements and designates an order in which the non-favored storage elements are evicted from the cache. The method also maintains one or more “favored” LRU lists that contain entries associated with favored storage elements and designate an order in which the favored storage elements are evicted from the cache. Each “favored” LRU list is associated with favored storage elements that have a different preferred residency time in the cache. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Kyler A. Anderson
  • Patent number: 11169919
    Abstract: A method for improving cache hit ratios for selected volumes within a storage system includes monitoring I/O to multiple volumes residing on a storage system. The method determines, from the I/O, which particular volumes of the multiple volumes would benefit the most if provided favored status in cache of the storage system, where the favored status provides increased residency time in the cache compared to volumes not having the favored status. The method determines, from the I/O, an amount by which the increased residency time should exceed a residency time of volumes not having the favored status. The method generates an indicator that is representative of the amount and transmits this indicator to the storage system. The storage system, in turn, provides increased residency time to the particular volumes in accordance with the favored status and indicator. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Beth A. Peterson, Kyler A. Anderson, Kevin J. Ash
  • Patent number: 11163697
    Abstract: Provided are techniques for using a memory subsystem for a workload job. A section of a memory subsystem is allocated to a workload job, where the memory subsystem is comprised of a plurality of heterogeneous memory devices. In response to a track being modified for the workload job in a cache, it is determined that modified tracks have reached a threshold portion of the cache. In response to determining that the track exists in the section of the memory subsystem, data in the track in the section of the memory subsystem is overwritten with data in the track in the cache. in response to determining that the track does not exist in the section of the memory subsystem, the data in the track in the cache is copied to the track in the section of the memory subsystem, and the track is demoted from the cache.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Kevin J. Ash, Kyler A. Anderson