Patents by Inventor Kevin J. Ash

Kevin J. Ash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11163698
    Abstract: A method for improving cache hit ratios for selected volumes when using synchronous I/O is disclosed. In one embodiment, such a method includes establishing, in cache, a first set of non-favored storage elements from non-favored storage areas. The method further establishes, in the cache, a second set of favored storage elements from favored storage areas. The method calculates a life expectancy for the non-favored storage elements to reside in the cache prior to eviction. The method further executes an eviction policy for the cache wherein the favored storage elements are maintained in the cache for longer than the life expectancy of the non-favored storage elements. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Beth A. Peterson, Kevin J. Ash, Kyler A. Anderson
  • Publication number: 20210334036
    Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Inventors: Trung N. Nguyen, Kevin J. Ash, Brian Anthony Rinaldi, Lokesh Mohan Gupta, Kyler A. Anderson
  • Patent number: 11157199
    Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trung N. Nguyen, Kevin J. Ash, Brian Anthony Rinaldi, Lokesh Mohan Gupta, Kyler A. Anderson
  • Patent number: 11157376
    Abstract: Provided are a computer program product, system, and method to transfer track format information for tracks in cache at a primary storage system to a secondary storage system to which tracks are mirrored to use after a failover or failback. In response to a failover from the primary storage system to the secondary storage system, the primary storage system adds a track identifier of the track and track format information indicating a layout of data in the track, indicated in track metadata for the track in the primary storage, to a cache transfer list. The primary storage system transfers the cache transfer list to the secondary storage system to use the track format information in the cache transfer list for a track staged into the secondary cache having a track identifier in the cache transfer list.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11150840
    Abstract: A method for pinning selected volumes within a heterogeneous cache is disclosed. The method maintains a heterogeneous cache made up of a higher performance portion and a lower performance portion. A list of pinned volumes is received that are provided higher priority than other volumes within the heterogeneous cache. The method dedicates, within the lower performance portion, a storage area to accommodate the pinned volumes and prestages the pinned volumes within the storage area. In certain embodiments, an LRU list is maintained that indicates an order in which storage elements of the pinned volumes are demoted from the storage area. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 9, 2020
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, Beth A. Peterson
  • Patent number: 11151035
    Abstract: A method for improving cache hit ratios for selected storage elements within a storage system is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a first LRU list containing entries associated with non-favored storage elements and designating an order in which the non-favored storage elements are evicted from the cache, and a second LRU list containing entries associated with favored storage elements and designating an order in which the favored storage elements are evicted from the cache. The method moves entries between the first LRU list and the second LRU list as favored storage elements are changed to non-favored storage elements and vice versa. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Beth A. Peterson, Kevin J. Ash, Kyler A. Anderson
  • Patent number: 11151037
    Abstract: Provided are a computer program product, system, and method for using track locks and stride group locks to manage cache operations. A group of tracks from the storage devices are stored in a cache. Exclusive track locks for tracks in the group in the cache are granted for writes to the tracks in the group in the cache, wherein exclusive track locks can be simultaneously held for writes to different tracks in the cache. An exclusive group lock for the group of tracks in the cache is granted to destage the tracks in the group from the cache to the storage devices. The exclusive group lock is released in response to completing the destage of the tracks in the group in the cache to the storage devices.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11151058
    Abstract: Provided are a computer program product, system, and method for staging data from storage to a fast cache tier of a multi-tier cache in a non-adaptive sector caching mode in which data staged in response to a read request is limited to track sectors required to satisfy the read request. Data is also staged from storage to a slow cache tier of the multi-tier cache in a selected adaptive caching mode of a plurality of adaptive caching modes available for staging data of tracks. Adaptive caching modes are selected for the slow cache tier as a function of historical access ratios. Prestage requests for the slow cache tier are enqueued in one of a plurality of prestage request queues of various priority levels as a function of the selected adaptive caching mode and historical access ratios. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 11144462
    Abstract: In one embodiment, a task control block (TCB) for allocating cache storage such as cache segments in a multi-track cache write operation may be enqueued in a wait queue for a relatively long wait period, the first time the task control block is used, and may be re-enqueued on the wait queue for a relatively short wait period, each time the task control block is used for allocating cache segments for subsequent cache writes of the remaining tracks of the multi-track cache write operation. As a result, time-out suspensions caused by throttling of host input-output operations to facilitate cache draining, may be reduced or eliminated. It is appreciated that wait classification of task control blocks in accordance with the present description may be applied to applications other than draining a cache. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew G. Borlick, Jared M. Minch
  • Patent number: 11144475
    Abstract: A computer program product, system, and method for managing adding of accessed tracks in cache to a most recently used end of a cache list. A cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track in the cache indicated on the cache list is accessed. A determination is made as to whether a track cache residency time since the accessed track was last accessed while in the cache list is within a region of lowest track cache residency times. A flag is set for the accessed track indicating to indicate the track at the MRU end in response to determining that the track cache residency time of the accessed track is within the region of lowest track cache residency times. The accessed track remains at a current position in the cache list before being accessed after setting the flag.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11144213
    Abstract: A metadata track stores metadata corresponding to both a first customer data track and a second customer data track. In response to receiving a first request to perform a write on the first customer data track from a two track write process, exclusive access to the first customer data track is provided to the first request, and shared access to the metadata track is provided to the first request. In response to receiving a second request to perform a write on the second customer data track from the two track write process, exclusive access to the second customer data track is provided to the second request, and shared access to the metadata track is provided to the second request prior to providing exclusive access to the metadata track to at least one process that is waiting for exclusive access to the metadata track.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 12, 2021
    Assignee: Intemational Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Jared M. Minch, Beth A. Peterson
  • Publication number: 20210286729
    Abstract: Provided are a computer program product, system, and method for using mirroring cache list to demote modified tracks from cache A modified track for a primary storage stored in the cache to mirror to a secondary storage is indicated in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks in the cache are transferred to the secondary storage. The mirroring cache list is processed to determine modified tracks in the cache to demote from the cache.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210286723
    Abstract: Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210286691
    Abstract: Provided are a computer program product, system, and method for using a mirroring cache list to mirror modified tracks for a primary storage in a cache to a secondary storage. Indication is made of a modified track for the primary storage stored in the cache in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks are transferred to the secondary storage. Indication of a modified track is removed from the mirroring cache list in response to demoting the modified track from the cache.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Patent number: 11119673
    Abstract: A method for dynamically adjusting utilization of I/O processing techniques includes providing functionality to execute a plurality of I/O processing techniques. The I/O processing techniques include a first I/O processing technique that uses a higher performance communication path for transmitting I/O and a second I/O processing technique that uses a lower performance communication path for transmitting I/O. The method automatically increases use of the first I/O processing technique and reduces use of the second I/O processing technique when the set of conditions is satisfied. Similarly, the method automatically increases use of the second I/O processing technique and reduces use of the first I/O processing technique when the set of conditions is not satisfied. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Kyler A. Anderson
  • Publication number: 20210279174
    Abstract: A computer-implemented method, according to one approach, includes: receiving a stream of incoming I/O requests, all of which are satisfied using one or more buffers in a primary cache. However, in response to determining that the available capacity of the one or more buffers in the primary cache is outside a predetermined range: one or more buffers in the secondary cache are allocated. These one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests, while the one or more buffers in the primary cache are used to satisfy a remainder of the incoming I/O requests. Moreover, in response to determining that the available capacity of the one or more buffers in the primary cache is not outside the predetermined range: the one or more buffers in the primary cache are again used to satisfy all of the incoming I/O requests.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Inventors: Beth Ann Peterson, Kevin J. Ash, Lokesh Mohan Gupta, Warren Keith Stanley, Roger G. Hathorn
  • Publication number: 20210279179
    Abstract: Provided are I/O request type specific cache directories in accordance with the present description. In one embodiment, by limiting track entries of a cache directory to a specific I/O request type, the size of the cache directory may be reduced as compared to general cache directories for I/O requests of all types, for example. As a result, look-up operations directed to such smaller size I/O request type specific cache directories may be completed in each directory more quickly. In addition, look-ups may frequently be successfully completed after a look-up of a single I/O request type specific cache directory, improving the speed of cache look-ups and providing a significant improvement in system performance. Other aspects and advantages are provided, depending upon the particular application.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventors: Gail SPEAR, Lokesh Mohan GUPTA, Kevin J. ASH, Kyler A. ANDERSON
  • Publication number: 20210271641
    Abstract: A method for improving asynchronous data replication between a primary storage system and a secondary storage system is disclosed. In one embodiment, such a method includes monitoring, in a cache of the primary storage system, unmirrored data elements needing to be mirrored, but that have not yet been mirrored, from the primary storage system to the secondary storage system. The method maintains a regular LRU list designating an order in which data elements are demoted from the cache. The method determines whether a data element at an LRU end of the regular LRU list is an unmirrored data element. In the event the data element at the LRU end of the regular LRU list is an unmirrored data element, the method moves the data element to a transfer-pending LRU list dedicated to unmirrored data elements in the cache. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Applicant: International Business Machines Corporation
    Inventors: Gail Spear, Lokesh M. Gupta, Kyler A. Anderson, David B. Schreiber, Kevin J. Ash
  • Publication number: 20210272022
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache by training a machine learning module. A machine learning module that receives as input performance attributes of system components affected by staging tracks from the storage to the cache and outputs a staging strategy comprising one of a plurality of staging strategy indicating at least one of a plurality of sectors of a track to stage into the cache. A margin of error is determined based on a current value of a performance attribute and a threshold of the performance attribute. An adjusted staging strategy is determined based on the margin of error. The machine learning module is retrained with current performance attributes to output the adjusted staging strategy.
    Type: Application
    Filed: May 13, 2021
    Publication date: September 2, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Publication number: 20210271638
    Abstract: A method for improving asynchronous data replication between a primary storage system and a secondary storage system maintains a cache in the primary storage system. The cache includes a higher performance portion and a lower performance portion. The method monitors, in the cache, unmirrored data elements needing to be mirrored, but that have not yet been mirrored, from the primary storage system to the secondary storage system. The method maintains a regular LRU list designating an order in which data elements are demoted from the cache. The method determines whether a data element at an LRU end of the regular LRU list is an unmirrored data element. In the event the data element at the LRU end is an unmirrored data element, the method moves the data element from the higher performance portion to the lower performance portion. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, Kyler A. Anderson