Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: An alignment module for housing and cleaning masks. The alignment module comprises a mask stocker, a cleaning chamber, an alignment chamber, an alignment stage a transfer robot. The mask stocker is configured to house a mask cassette configured to store a plurality of masks. The cleaning chamber is configured to clean the plurality of masks by providing one or more cleaning gases into a chamber after a mask is inserted into the cleaning chamber. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer a mask from one or more of the alignment stage and the mask stocker to the cleaning chamber.

Abstract: Generally, examples described herein relate to deposition masks and methods of manufacturing and using such deposition masks. An example includes a method for forming a deposition mask. A mask layer is deposited on a substrate. Mask openings are patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a periphery portion of the substrate. The mask layer with the mask openings through the mask layer extending across the substrate opening.

Abstract: An alignment module for positioning a mask on a substrate comprises a mask stocker, an alignment stage, and a transfer robot. The mask stocker houses a mask cassette that stores a plurality of masks. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer one of the one or more masks from the mask stocker to the alignment stage and position the mask over the substrate. The alignment module may be part of an integrated platform having one or more transfer chambers, a factory interface having a substrate carrier chamber and one or more processing chambers. A carrier may be coupled to a substrate within the substrate carrier chamber and moved between the processing chambers to generate a semiconductor device.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: Substrate carrier apparatus having a hard mask are disclosed herein. In some embodiments, a substrate carrier apparatus includes a carrier body having a support surface to support a substrate; and a mask assembly disposed above the support surface. The mask assembly includes an annular frame disposed atop the support surface; and a hard mask coupled to and disposed within the annular frame above the support surface, wherein the hard mask includes one or more openings arranged in a predetermined pattern and disposed through the hard mask, and wherein the hard mask includes a plurality of spacer elements extending from a bottom surface of the hard mask.

Abstract: An alignment module for positioning a mask on a substrate comprises a mask stocker, an alignment stage, and a transfer robot. The mask stocker houses a mask cassette that stores a plurality of masks. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer one of the one or more masks from the mask stocker to the alignment stage and position the mask over the substrate. The alignment module may be part of an integrated platform having one or more transfer chambers, a factory interface having a substrate carrier chamber and one or more processing chambers. A carrier may be coupled to a substrate within the substrate carrier chamber and moved between the processing chambers to generate a semiconductor device.

Abstract: An alignment module for housing and cleaning masks. The alignment module comprises a mask stocker, a cleaning chamber, an alignment chamber, an alignment stage a transfer robot. The mask stocker is configured to house a mask cassette configured to store a plurality of masks. The cleaning chamber is configured to clean the plurality of masks by providing one or more cleaning gases into a chamber after a mask is inserted into the cleaning chamber. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer a mask from one or more of the alignment stage and the mask stocker to the cleaning chamber.

Abstract: Generally, examples described herein relate to deposition masks and methods of manufacturing and using such deposition masks. An example includes a method for forming a deposition mask. A mask layer is deposited on a substrate. Mask openings are patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a periphery portion of the substrate. The mask layer with the mask openings through the mask layer extending across the substrate opening.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: Substrate carrier apparatus having a hard mask are disclosed herein. In some embodiments, a substrate carrier apparatus includes a carrier body having a support surface to support a substrate; and a mask assembly disposed above the support surface. The mask assembly includes an annular frame disposed atop the support surface; and a hard mask coupled to and disposed within the annular frame above the support surface, wherein the hard mask includes one or more openings arranged in a predetermined pattern and disposed through the hard mask, and wherein the hard mask includes a plurality of spacer elements extending from a bottom surface of the hard mask.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: Methods to selectively deposit capping layers on a copper surface relative to a dielectric surface comprising separately the copper surface to a cobalt precursor gas and a tungsten precursor gas, each in a separate processing chamber. The copper surface and the dielectric surfaces can be substantially coplanar. The combined thickness of cobalt and tungsten capping films is in the range of about 2 ? to about 60 ?.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: An integrated extreme ultraviolet blank production system includes: a vacuum chamber for placing a substrate in a vacuum; a deposition system for depositing a multi-layer stack without removing the substrate from the vacuum; and a treatment system for treating a layer on the multi-layer stack to be deposited as an amorphous metallic layer. A physical vapor deposition chamber for manufacturing an extreme ultraviolet mask blank includes: a target, comprising molybdenum alloyed with boron. An extreme ultraviolet lithography system includes: an extreme ultraviolet light source; a mirror for directing light from the extreme ultraviolet light source; a reticle stage for placing an extreme ultraviolet mask blank with a multi-layer stack having an amorphous metallic layer; and a wafer stage for placing a wafer. An extreme ultraviolet blank includes: a substrate; a multi-layer stack having an amorphous metallic layer; and capping layers over the multi-layer stack.

Abstract: A method and apparatus for forming a magnetic layer having a pattern of magnetic properties on a substrate is described. The method includes using a metal nitride hardmask layer to pattern the magnetic layer by plasma exposure. The metal nitride layer is patterned using a nanoimprint patterning process with a silicon oxide pattern negative material. The pattern is developed in the metal nitride using a halogen and oxygen containing remote plasma, and is removed after plasma exposure using a caustic wet strip process. All processing is done at low temperatures to avoid thermal damage to magnetic materials.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: An integrated extreme ultraviolet blank production system includes: a vacuum chamber for placing a substrate in a vacuum; a deposition system for depositing a multi-layer stack without removing the substrate from the vacuum; and a treatment system for treating a layer on the multi-layer stack to be deposited as an amorphous metallic layer. A physical vapor deposition chamber for manufacturing an extreme ultraviolet mask blank includes: a target, comprising molybdenum alloyed with boron. An extreme ultraviolet lithography system includes: an extreme ultraviolet light source; a mirror for directing light from the extreme ultraviolet light source; a reticle stage for placing an extreme ultraviolet mask blank with a multi-layer stack having an amorphous metallic layer; and a wafer stage for placing a wafer. An extreme ultraviolet blank includes: a substrate; a multi-layer stack having an amorphous metallic layer; and capping layers over the multi-layer stack.