Patents by Inventor Kevin P. Grundy

Kevin P. Grundy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110171857
    Abstract: An electrical connector. An electrical connector comprising a connector body having a first channel and a first conductive element extending through the first channel in a first tip section. The first tip section having a first moment arm that, when forced in contact with a first conductive surface, twists the first conductive element to produce a torsion force. The torsion force holds the first tip section in contact with the first conductive surface.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 14, 2011
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Gary Yasumura, William F. Wiedemann, Joseph C. Fjelstad, Para K. Segaram, Kevin P. Grundy
  • Patent number: 7973391
    Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Gary Yasumura
  • Patent number: 7966443
    Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kevin P. Grundy, Para K. Segaram
  • Patent number: 7919355
    Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: April 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber, legal representative, Kevin P. Grundy
  • Patent number: 7909615
    Abstract: An electrical connector. An electrical connector comprising a connector body having a first channel and a first conductive element extending through the first channel in a first tip section. The first tip section having a first moment arm that, when forced in contact with a first conductive surface, twists the first conductive element to produce a torsion force. The torsion force holds the first tip section in contact with the first conductive surface.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: March 22, 2011
    Assignee: Interconnect Portfolio LLC
    Inventors: Gary Yasumura, Kevin P. Grundy, William F. Wiedemann, Joseph C. Fjelstad, Para K. Segaram
  • Publication number: 20110065332
    Abstract: An electrical connector. An electrical connector comprising a connector body having a first channel and a first conductive element extending through the first channel in a first tip section. The first tip section having a first moment arm that, when forced in contact with a first conductive surface, twists the first conductive element to produce a torsion force. The torsion force holds the first tip section in contact with the first conductive surface.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Gary Yasumura, William F. Wiedemann, Joseph C. Fjelstad, Para K. Segaram, Kevin P. Grundy
  • Patent number: 7845986
    Abstract: An electrical connector. An electrical connector comprising a connector body having a first channel and a first conductive element extending through the first channel in a first tip section. The first tip section having a first moment arm that, when forced in contact with a first conductive surface, twists the first conductive element to produce a torsion force. The torsion force holds the first tip section in contact with the first conductive surface.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: December 7, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Gary Yasumura, William F. Wiedemann, Joseph C. Fjelstad, Para K. Segaram, Kevin P. Grundy
  • Patent number: 7837477
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gary Yasamura, Joseph C. Fjelstad, Kevin P. Grundy, William F. Wiedemann, Matthew J. Stepovich
  • Publication number: 20100284115
    Abstract: An ESD device with a protection structure utilizing radiated heat dissipation to prevent or reduce thermal failures. The device includes a voltage switchable polymer 10 between electrodes 11 and 12, which is configured to provide a heat radiating surface 40 for radiating heat when an ESD condition occurs. A radiation transmission material 19 is disposed between the heat radiating surface and the environment for radiating heat 20 when an ESD event occurs. One embodiment adds a spacer 50 for accurately spacing electrodes. A method for fabricating the device is further illustrated.
    Type: Application
    Filed: May 5, 2009
    Publication date: November 11, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Kevin P. Grundy, Joseph C. Fjelstad
  • Publication number: 20100221871
    Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Kevin P. Grundy, Inessa Obenhuber
  • Patent number: 7750446
    Abstract: Disclosed are IC package structures comprised of standard IC packages modified with separate circuit interconnection structures and disposed to interconnect either directly to other IC packages or to intermediate pedestal connectors which serve to support and interconnect various circuit elements, thus effectively allowing critical signals to bypass the generally less capable interconnection paths within standard interconnection substrates.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: July 6, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Gary Yasumura
  • Publication number: 20100165525
    Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 1, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, William F. Wiedemann, Thomas J. Obenhuber, Inessa Obenhuber
  • Publication number: 20100151704
    Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.
    Type: Application
    Filed: January 25, 2010
    Publication date: June 17, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram, Kevin P. Grundy
  • Patent number: 7737545
    Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: June 15, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber, legal representative, Kevin P. Grundy
  • Patent number: 7732904
    Abstract: A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: June 8, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber, legal representative, Kevin P. Grundy, William F. Wiedemann
  • Publication number: 20100127402
    Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 27, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Kevin P. Grundy, Joseph C. Fjelstad, Gary Yasumura, William F. Wiedemann, Para K. Segaram
  • Publication number: 20100112829
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Application
    Filed: January 4, 2010
    Publication date: May 6, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Gary Yasamura, Joseph C. Fjelstad, Kevin P. Grundy, William F. Wiedemann, Matthew J. Stepovich
  • Patent number: 7701323
    Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: April 20, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, William F. Wiedemann, Thomas J. Obenhuber, Inessa Obenhuber, legal representative
  • Patent number: 7651336
    Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: January 26, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram, Kevin P. Grundy
  • Patent number: 7651382
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 26, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, Kevin P. Grundy, William F. Wiedemann, Matthew J. Stepovich