Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.

Abstract: An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed

Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.

Abstract: A memory system having a memory controller, interface device and plurality of memory elements. The interface device is coupled to the memory controller via a first high-speed signal path. The plurality of memory elements are removably coupled to the interface device via respective second signal paths, each of the second signal paths having a lower signaling bandwidth than the first signaling path.

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract: A memory system having a memory controller, interface device and plurality of memory elements. The interface device is coupled to the memory controller via a first high-speed signal path. The plurality of memory elements are removably coupled to the interface device via respective second signal paths, each of the second signal paths having a lower signaling bandwidth than the first signaling path.

Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

Abstract: An apparatus for communicating with a communication network includes a processor, communication circuitry that interfaces with a communication network, and a bus connecting the processor to the communication circuitry. A port is connected to the bus, which communicates using an external communication protocol specified by a peripheral device. A memory, comprising a translator module that converts signals between the external communication protocol and an internal communication protocol operates such that communication signals transmitted to the port are converted from the internal communication protocol to the external communication protocol and signals received by the port are converted from the external communication protocol to the internal communication protocol.

Abstract: A switching device and method for selecting among a plurality of hosts on a bus, such as a Universal Serial Bus (USB). The switching device includes a first hub to be coupled to first host controller and a second hub to be coupled to second host controller. A first selection device is to be coupled to a first peripheral device and the first and second hub devices. The first selection device is to selectively couple the first peripheral device to one of the first and second host devices in response to a selection signal. A second selection device is to be coupled to a second peripheral device and the first and second hub devices. The second selection device is to selectively couple the second peripheral device to one of the first and second host controllers in response to the selection signal. The selection signal is generated in response to one of the host controllers.

Abstract: A method and an apparatus for providing data communications over the existing telephone network without burdening the public switched telephone network (PSTN) switch with data communications traffic. In one embodiment, a novel modem is coupled to both ends of the twisted pair telephone wire which runs between a remote location and the Central Office (CO) or the remote CO. An off-hook detector is also connected to the twisted pair line in order to enable detection of when normal telephony functions are being performed over the twisted pair line. The modems of the present invention are capable of transmitting data whenever normal telephony functions are not being performed, such as for example when the telephone line is on-hook. The data transmission in accordance with the teachings of the present invention uses sufficiently low current levels such that the PSTN switch located at the CO does not detect any activity on the twisted pair line.

Abstract: A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.

Abstract: In a computer system equipped with a magneto-optical disk drive having high data density, and therefore lengthy format times, and also requiring an erase step before each write operation, a system and method for decreasing user waiting time is provided. The system and method format the disk on a continuous basis during "disk-idle" periods rather than all at once. The system and method also erase disk portions belonging to deleted data in advance during disk-idle periods, so they are ready for the next write operation.

Abstract: In a computer system equipped with a magneto-optical disk drive having high data density, and therefore lengthy format times, and also requiring an erase step before each write operation, a system and method for decreasing user waiting time is provided. The system and method format the disk on a continuous basis during "disk-idle" periods rather than all at once. The system and method also erase disk portion belonging to deleted data in advance during disk-idle periods, so they are ready for the next write operation.