Patents by Inventor Kezhakkedath R. Udayakumar
Kezhakkedath R. Udayakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10665543Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.Type: GrantFiled: June 18, 2018Date of Patent: May 26, 2020Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
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Publication number: 20180308802Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.Type: ApplicationFiled: June 18, 2018Publication date: October 25, 2018Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
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Patent number: 10008450Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.Type: GrantFiled: June 7, 2017Date of Patent: June 26, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
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Publication number: 20170271269Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.Type: ApplicationFiled: June 7, 2017Publication date: September 21, 2017Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
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Patent number: 9704804Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.Type: GrantFiled: December 18, 2015Date of Patent: July 11, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
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Publication number: 20170179033Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
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Patent number: 9548377Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.Type: GrantFiled: May 9, 2014Date of Patent: January 17, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. Udayakumar, Kemal Tamer San
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Publication number: 20150079698Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.Type: ApplicationFiled: May 9, 2014Publication date: March 19, 2015Applicant: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Kemal Tamer San
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Patent number: 8778700Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.Type: GrantFiled: February 19, 2013Date of Patent: July 15, 2014Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
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Patent number: 8779485Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.Type: GrantFiled: May 24, 2012Date of Patent: July 15, 2014Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
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Patent number: 8723241Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.Type: GrantFiled: July 19, 2013Date of Patent: May 13, 2014Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Marie Denison, Theodore S. Moise
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Publication number: 20130307375Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.Type: ApplicationFiled: July 19, 2013Publication date: November 21, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. Udayakumar, Marie Denison, Theodore S. Moise
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Patent number: 8496842Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.Type: GrantFiled: September 12, 2011Date of Patent: July 30, 2013Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Marie Denison, Ted S. Moise
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Patent number: 8440508Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.Type: GrantFiled: March 5, 2010Date of Patent: May 14, 2013Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
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Publication number: 20130062996Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. Udayakumar, Marie Denison, Ted S. Moise
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Publication number: 20120228739Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.Type: ApplicationFiled: May 24, 2012Publication date: September 13, 2012Applicant: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
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Patent number: 8093070Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: GrantFiled: February 15, 2007Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Patent number: 8071430Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.Type: GrantFiled: January 14, 2011Date of Patent: December 6, 2011Assignee: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Kezhakkedath R. Udayakumar, John P. Campbell, Hugh P. McAdams
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Patent number: 8058677Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.Type: GrantFiled: March 3, 2009Date of Patent: November 15, 2011Assignee: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Kezhakkedath R. Udayakumar, John P. Campbell, Hugh P. McAdams
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Patent number: 8053252Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: GrantFiled: July 14, 2009Date of Patent: November 8, 2011Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt