Patents by Inventor Kezhakkedath R. Udayakumar
Kezhakkedath R. Udayakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110183471Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.Type: ApplicationFiled: January 14, 2011Publication date: July 28, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott R. Summerfelt, Kezhakkedath R. Udayakumar, John P. Campbell, Hugh P. McAdams
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Patent number: 7985603Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: GrantFiled: February 4, 2008Date of Patent: July 26, 2011Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Patent number: 7935543Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.Type: GrantFiled: May 26, 2009Date of Patent: May 3, 2011Assignee: Texas Instruments IncorporatedInventors: Theodore S. Moise, IV, Scott R. Summerfelt, Kezhakkedath R. Udayakumar
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Publication number: 20110062550Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.Type: ApplicationFiled: March 5, 2010Publication date: March 17, 2011Applicant: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
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Publication number: 20100270601Abstract: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.Type: ApplicationFiled: July 1, 2010Publication date: October 28, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. Udayakumar, Ted S. Moise, Qi-Du Jiang
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Patent number: 7799582Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: GrantFiled: July 14, 2009Date of Patent: September 21, 2010Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
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Patent number: 7772014Abstract: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.Type: GrantFiled: August 28, 2007Date of Patent: August 10, 2010Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Ted S. Moise, Qi-Du Jiang
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Patent number: 7723199Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: GrantFiled: January 31, 2007Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
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Publication number: 20090275147Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: ApplicationFiled: July 14, 2009Publication date: November 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. UDAYAKUMAR, Lindsey H. HALL, Francis G. CELII, Scott R. SUMMERFELT
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Publication number: 20090275148Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: ApplicationFiled: July 14, 2009Publication date: November 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. UDAYAKUMAR, Lindsey H. HALL, Francis G. CELII
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Patent number: 7572698Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: GrantFiled: May 30, 2006Date of Patent: August 11, 2009Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
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Publication number: 20090194801Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: ApplicationFiled: February 4, 2008Publication date: August 6, 2009Applicant: Texas Instruments Inc.Inventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Publication number: 20090057736Abstract: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.Type: ApplicationFiled: August 28, 2007Publication date: March 5, 2009Applicant: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Ted S. Moise, Qi-Du Jiang
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Patent number: 7425512Abstract: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.Type: GrantFiled: November 25, 2003Date of Patent: September 16, 2008Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Ted S. Moise, Scott R. Summerfelt, Martin G. Albrecht, William W. Dostalik, Jr., Francis G. Celii
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Publication number: 20080081380Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: ApplicationFiled: February 15, 2007Publication date: April 3, 2008Inventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Publication number: 20070298521Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: ApplicationFiled: January 31, 2007Publication date: December 27, 2007Applicant: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
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Publication number: 20070281422Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: ApplicationFiled: May 30, 2006Publication date: December 6, 2007Inventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
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Patent number: 7304881Abstract: Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the ferroelectric memory device which are associated with a single polarization direction, thereby allowing for a single cell to contain more than one bit of data.Type: GrantFiled: June 28, 2004Date of Patent: December 4, 2007Assignee: Texas Instruments IncorporatedInventors: John Anthony Rodriguez, Kezhakkedath R. Udayakumar
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Patent number: 7220600Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.Type: GrantFiled: December 17, 2004Date of Patent: May 22, 2007Assignee: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Lindsey H. Hall, Kezhakkedath R. Udayakumar, Theodore S. Moise, IV
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Patent number: 7085150Abstract: The present invention facilitates data retention lifetimes for ferroelectric devices by improving switched polarization of ferroelectric memory cells. A ferroelectric memory device comprising ferroelectric memory cells is provided (702). A duration for applying a DC bias to the ferroelectric memory cells is selected (704) according to at least a desired switched polarization improvement. A magnitude for applying the DC bias to the ferroelectric memory cells is also selected (706) according to at least the desired switched polarization improvement. Further, an elevated temperature is selected for applying the DC bias to the ferroelectric memory cells is also selected (708) according to at least the desired switched polarization improvement. Subsequently, the DC bias is applied to the ferroelectric memory cells (710), which activates one or more inactive domains within the ferroelectric memory cells and increases initial polarization values.Type: GrantFiled: December 20, 2004Date of Patent: August 1, 2006Assignee: Texas Instruments IncorporatedInventors: John A. Rodriguez, Kezhakkedath R. Udayakumar