Abstract: The present disclosure relates to a lead halide perovskite (LHP) synthesis simulation method, and more particularly to an LHP synthesis simulation method that minimizes a change in wavelength of light emitted from an LHP material when exposed to light for a predetermined time.

Abstract: The present disclosure relates to a lead halide perovskite (LHP) synthesis simulation method, and more particularly to an LHP synthesis simulation method that minimizes a change in wavelength of light emitted from an LHP material when exposed to light for a predetermined time.

Abstract: Various aspects of the present invention are directed to providing a perovskite solar cell, and has a technical feature in that excellent stability and high efficiency are simultaneously secured by using a solid solution having a specific composition as a light absorber.

Abstract: Various aspects of the present invention are directed to providing a perovskite solar cell, and has a technical feature in that excellent stability and high efficiency are simultaneously secured by using a solid solution having a specific composition as a light absorber.

Abstract: A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer.

Abstract: High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain, a gate, a channel supplying layer for forming at least a 2-dimensional electron gas (2DEG) channel, and a channel formation layer in which at least the 2DEG channel is formed. The channel supplying layer includes a plurality of semiconductor layers having different polarizabilities. A portion of the channel supplying layer is recessed. One of the plurality of semiconductor layers, which is positioned below an uppermost layer is an etching buffer layer, as well as a channel supplying layer.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

Abstract: High electron mobility transistors (HEMTs) including a cavity below a drain and methods of manufacturing HEMTS including removing a portion of a substrate below a drain.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer.

Abstract: High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer.

Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.