Patents by Inventor Ki-ha Hong
Ki-ha Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130119347Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.Type: ApplicationFiled: September 12, 2012Publication date: May 16, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-jin CHO, Kyoung-yeon KIM, Sang-moon LEE, Ki-ha HONG, Eui-chul HWANG
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Patent number: 8385098Abstract: A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.Type: GrantFiled: September 3, 2010Date of Patent: February 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-ha Hong, Jeong-seob Kim, Jai-kwang Shin
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Publication number: 20130032816Abstract: High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer.Type: ApplicationFiled: March 27, 2012Publication date: February 7, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Hyuk-soon Choi, Jae-joon Oh, Jong-bong Ha, Jong-seob Kim, Ki-ha Hong, Jai-kwang Shin
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Patent number: 8357992Abstract: The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines.Type: GrantFiled: March 11, 2010Date of Patent: January 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-jung Kim, In-kyeong Yoo, Chang-jung Kim, Ki-ha Hong
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Publication number: 20130001587Abstract: High electron mobility transistors (HEMTs) including a cavity below a drain and methods of manufacturing HEMTS including removing a portion of a substrate below a drain.Type: ApplicationFiled: June 27, 2012Publication date: January 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Ki-ha Hong, Jae-joon Oh, Jong-bong Ha, Jong-seob Kim, Hyuk-soon Choi, Jai-kwang Shin
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Publication number: 20120280244Abstract: High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a channel layer and a channel supply layer, and the channel supply layer may be a multilayer structure. The channel supply layer may include an etch stop layer and an upper layer on the etch stop layer. A recess region may be in the upper layer. The recess region may be a region recessed to an interface between the upper layer and the etch stop layer. A gate electrode may be on the recess region.Type: ApplicationFiled: November 30, 2011Publication date: November 8, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-bong Ha, Hyuk-soon Choi, Ki-ha Hong
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Patent number: 8293554Abstract: A luminous device and a method of manufacturing the luminous device are provided. The luminous device includes a light emitting layer and first and second electrodes connected to the light emitting layer. The light emitting layer is a strained nanowire.Type: GrantFiled: September 16, 2009Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-ha Hong, Sung-hoon Lee, Jong-seob Kim, Jai-kwang Shin
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Patent number: 8269293Abstract: Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on.Type: GrantFiled: November 4, 2008Date of Patent: September 18, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Ha Hong, Sung-Hoon Lee, Jong-Seob Kim, Jai-Kwang Shin
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Patent number: 8263449Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.Type: GrantFiled: January 31, 2011Date of Patent: September 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-ha Hong, U-In Chung, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, In-jun Hwang
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Patent number: 8203863Abstract: A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor.Type: GrantFiled: June 14, 2010Date of Patent: June 19, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-jung Kim, In-kyeong Yoo, Jai-kwang Shin, Chang-jung Kim, Myoung-jae Lee, Ki-ha Hong
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Publication number: 20120112202Abstract: An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.Type: ApplicationFiled: July 11, 2011Publication date: May 10, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Ki-ha Hong, Jong-seob Kim, Jae-Kwang Shin, Jae-joon Oh, Jong-bong Ha, Hyuk-soon Choi
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Publication number: 20120086049Abstract: According to an example embodiment, a high electron mobility transistor (HEMT) includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier structure on the channel layer. The buffer layer includes a 2-dimensional electron gas (2DEG). A polarization of the barrier structure varies in a region corresponding to a gate electrode. The HEMT further includes and the gate electrode, a source electrode, and a drain electrode on the barrier structure.Type: ApplicationFiled: August 31, 2011Publication date: April 12, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong, Jai-kwang Shin, Jae-joon Oh
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Publication number: 20120088341Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.Type: ApplicationFiled: July 8, 2011Publication date: April 12, 2012Applicants: Kyungpook National University Industry-Academic Cooperation Foundation, SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuk-soon Choi, Jung-hee Lee, Jai-kwang Shin, Jae-joon Oh, Jong-bong Ha, Jong-seob Kim, In-jun Hwang, Ki-ha Hong, Ki-sik Im, Ki-won Kim, Dong-seok Kim
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Patent number: 8119480Abstract: A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.Type: GrantFiled: September 29, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hoon Lee, Sungil Park, Young-Gu Jin, Jongseob Kim, Ki-Ha Hong
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Publication number: 20120037958Abstract: According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.Type: ApplicationFiled: August 12, 2011Publication date: February 16, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong
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Publication number: 20110303952Abstract: A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.Type: ApplicationFiled: June 2, 2011Publication date: December 15, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong
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Publication number: 20110273221Abstract: A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.Type: ApplicationFiled: March 15, 2011Publication date: November 10, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Ho-jung Kim, Jae-kwang Shin, Jae-Joon Oh, Jong-seob Kim, Hyuk-soon Choi, In-jun Hwang, Ki-ha Hong
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Publication number: 20110272743Abstract: High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain, a gate, a channel supplying layer for forming at least a 2-dimensional electron gas (2DEG) channel, and a channel formation layer in which at least the 2DEG channel is formed. The channel supplying layer includes a plurality of semiconductor layers having different polarizabilities. A portion of the channel supplying layer is recessed. One of the plurality of semiconductor layers, which is positioned below an uppermost layer is an etching buffer layer, as well as a channel supplying layer.Type: ApplicationFiled: April 28, 2011Publication date: November 10, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong
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Publication number: 20110221482Abstract: Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.Type: ApplicationFiled: October 12, 2010Publication date: September 15, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Ho-jung Kim, Jong-seob Kim, Jai-Kwang Shin, Jae-joon Oh, Ki-ha Hong, In-jun Hwang, Hyuk-soon Choi
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Publication number: 20110215378Abstract: High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer.Type: ApplicationFiled: January 28, 2011Publication date: September 8, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: In-Jun Hwang, Jong-Seob Kim, Hyuk-Soon Choi, Ki-Ha Hong, Jai-Kwang Shin, Jae-Joon Oh