Abstract: A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

Abstract: An in-line package apparatus includes a first treating unit, an input storage unit, a heating unit and an output storage unit. The first treating unit performs a ball attach process or a chip mount process. A processing object that a process is completed in the first treating unit is received in a magazine so as to be vertically stacked and a plurality of magazines each having one or more processing objects is stored in an input stacker. The heating unit performs a reflow process on the processing objects in the magazine stored in the input stacker by an induction heating method. A processing object that a reflow process is completed is received in a magazine and then stored in an output stacker.

Abstract: A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

Abstract: A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.

Abstract: An apparatus for processing a wafer includes a chamber, a boat, microwave generators and reflective plates. The boat is disposed in the chamber. One or more wafers are stacked in the boat. One or more microwave generators are connected to the chamber. The microwave generators generate microwaves for heating the wafers. The reflective plates reflect the microwaves onto the wafers such that the microwaves are uniformly applied to the wafers. Each of the reflective plates faces at least one of both sides of the wafer. The reflective plates include at least one of a fat side, a concave side and a convex side.

Abstract: A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.

Abstract: A method of inspecting the alignment of a second structure with respect to a first structure, including emitting light from a first plane of a first structure to a second plane of a second structure in a first direction perpendicular to the first plane of the first structure, the first plane and the second plane facing each other. The incident light can be reflected from the second plane toward the first plane in a second direction parallel with the first direction. The position of the reflected light can be detected to inspect the alignment of the second structure with respect to the first structure.

Abstract: Provided are a reflow apparatus and method. The reflow apparatus includes a loader unit, a heating unit, an unloader unit, and a moving unit. The loader unit has an input module and an input stacker. Processing objects are stored in vertical stacks in magazines, and a plurality of magazines is stored in the input stacker. The magazines stored in the input stacker are moved to the input module and are introduced into the heating unit by the moving unit. Solder balls provided on the processing objects within the heating unit are quickly processed using an induction heating method. The processing objects that have undergone a reflow process are loaded in a magazine on an output module of the unloader unit and are then stored in an output stacker.

Abstract: An in-line package apparatus includes a first treating unit, an input storage unit, a heating unit and an output storage unit. The first treating unit performs a ball attach process or a chip mount process. A processing object that a process is completed in the first treating unit is received in a magazine so as to be vertically stacked and a plurality of magazines each having one or more processing objects is stored in an input stacker. The heating unit performs a reflow process on the processing objects in the magazine stored in the input stacker by an induction heating method. A processing object that a reflow process is completed is received in a magazine and then stored in an output stacker.

Abstract: A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.

Abstract: A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.

Abstract: Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.

Abstract: A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed thereon, and then the wafer is cut to separate the chips from one another. Each semiconductor chip is then placed on and attached to a die pad of a base frame, while the warpage prevention material is detached from the semiconductor chip. Thus, the warpage prevention material is removed without requiring a process that is extraneous to the die attaching process.

Abstract: A method of utilizing a removable protective tape to protect the active surfaces of semiconductor wafer and the individual semiconductor chips during semiconductor packaging processes is provided along with several configurations of apparatuses that may be used in such a method for removing protective tape portions from individual semiconductor chips during the assembly process.

Abstract: Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus includes a plating unit that is disposed in a direction to form a conductive plating layer on external terminals of the semiconductor chip package; and a reflow unit that is disposed with the plating unit to melt the conductive plating layer. The packaging apparatus may further include a rinsing unit that is disposed with the plating unit to clean and cool the conductive plating layer. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.

Abstract: A dicing tape attaching unit that can attach both a pre-cut dicing tape and a general dicing tape to a wafer in a semiconductor package assembling process, and an in-line system used in a semiconductor package process including the dicing tape attaching unit are provided. The dicing tape attaching unit supplies one of the pre-cut dicing tape and the general dicing tape and attaches it to a wafer according to the direction of rotation of a tape loader. Accordingly, without an additional pre-cut dicing tape attaching unit, either of the pre-cut dicing tape and the general dicing tape can be attached to the back side of the wafer by one and the same unit.

Abstract: A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.

Abstract: Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus may include a plating unit to perform a conductive plating process to form a conductive plating layer on external terminals of a semiconductor chip package, and a reflow unit adapted to melt the conductive plating layer. The plating unit and reflow unit may be disposed in a single line with the plating module. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.

Abstract: A dicing tape attaching unit that can attach both a pre-cut dicing tape and a general dicing tape to a wafer in a semiconductor package assembling process, and an in-line system used in a semiconductor package process including the dicing tape attaching unit are provided. The dicing tape attaching unit supplies one of the pre-cut dicing tape and the general dicing tape and attaches it to a wafer according to the direction of rotation of a tape loader. Accordingly, without an additional pre-cut dicing tape attaching unit, either of the pre-cut dicing tape and the general dicing tape can be attached to the back side of the wafer by one and the same unit.

Abstract: A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed thereon, and then the wafer is cut to separate the chips from one another. Each semiconductor chip is then placed on and attached to a die pad of a base frame, while the warpage prevention material is detached from the semiconductor chip. Thus, the warpage prevention material is removed without requiring a process that is extraneous to the die attaching process.