Patents by Inventor Ki-Kwon Jeong

Ki-Kwon Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050282374
    Abstract: A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.
    Type: Application
    Filed: June 2, 2005
    Publication date: December 22, 2005
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeon Hwang, Ki-Kwon Jeong
  • Patent number: 6923077
    Abstract: An automatic wafer backside inspection may automatically inspect a backside of a semiconductor wafer to look for contamination, cracks, scratches and the like. An inspection apparatus may comprise a wafer cassette with slots to hold a plurality of wafers. A wafer transfer arm may be located near the wafer cassette. A wafer flip/aligner may be operable to flip and align wafers. A wafer inspecting unit may be located adjacent the wafer flip/aligner and be operable to inspect the backside of wafers flipped by the flipper aligner. A wafer buffer stage may be located between the wafer cassette and the wafer flip/aligner for temporarily holding a wafer. The wafer transfer arm may transfer wafers to/from or amongst at least two of the wafer cassette, the wafer flip/aligner, the wafer inspection unit and the wafer buffer stage.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: August 2, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kuk Kim, Seung-Bae Jeong, Ki-Kwon Jeong
  • Publication number: 20050153522
    Abstract: Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.
    Type: Application
    Filed: September 20, 2004
    Publication date: July 14, 2005
    Inventors: Hyeon Hwang, Dong-Kuk Kim, Ki-Kwon Jeong
  • Publication number: 20040121514
    Abstract: A method of utilizing a removable protective tape to protect the active surfaces of semiconductor wafer and the individual semiconductor chips during semiconductor packaging processes is provided along with several configurations of apparatuses that may be used in such a method for removing protective tape portions from individual semiconductor chips during the assembly process.
    Type: Application
    Filed: July 18, 2003
    Publication date: June 24, 2004
    Inventors: Cheol-Joon Yoo, Ki-Kwon Jeong
  • Publication number: 20040009650
    Abstract: A dicing tape attaching unit that can attach both a pre-cut dicing tape and a general dicing tape to a wafer in a semiconductor package assembling process, and an in-line system used in a semiconductor package process including the dicing tape attaching unit are provided. The dicing tape attaching unit supplies one of the pre-cut dicing tape and the general dicing tape and attaches it to a wafer according to the direction of rotation of a tape loader. Accordingly, without an additional pre-cut dicing tape attaching unit, either of the pre-cut dicing tape and the general dicing tape can be attached to the back side of the wafer by one and the same unit.
    Type: Application
    Filed: June 27, 2003
    Publication date: January 15, 2004
    Inventors: Ki-Kwon Jeong, Dong-Kuk Kim
  • Publication number: 20030159528
    Abstract: An automatic wafer backside inspection may automatically inspect a backside of a semiconductor wafer to look for contamination, cracks, scratches and the like. An inspection apparatus may comprise a wafer cassette with slots to hold a plurality of wafers. A wafer transfer arm may be located near the wafer cassette. A wafer flip/aligner may be operable to flip and align wafers. A wafer inspecting unit may be located adjacent the wafer flip/aligner and be operable to inspect the backside of wafers flipped by the flipper aligner. A wafer buffer stage may be located between the wafer cassette and the wafer flip/aligner for temporarily holding a wafer. The wafer transfer arm may transfer wafers to/from or amongst at least two of the wafer cassette, the wafer flip/aligner, the wafer inspection unit and the wafer buffer stage.
    Type: Application
    Filed: October 29, 2002
    Publication date: August 28, 2003
    Applicant: Samsung Electronics
    Inventors: Dong-Kuk Kim, Seung-Bae Jeong, Ki-Kwon Jeong
  • Patent number: 5898226
    Abstract: A semiconductor chip is provided comprising a semiconductor substrate having determined circuit elements on it, a surface-smoothing layer deposited on the substrate, a bonding pad formed on the smoothing layer and connected electrically to the circuit elements, a passivation layer formed on the surface-smoothing layer, the passivation layer having a window for exposing a part of the bonding pad, and a second metal layer having a same height as the passivation layer and occupying peripheral parts of the window to form a reduced bonding windows for the bonding pad.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: April 27, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Kwon Jeong, Hyeong-Seob Kim