Abstract: A Radio Frequency (RF) receiver is provided. The RF receiver is configured to simultaneously receive at least two radio frequency bands with a single receiver path. The RF receiver comprises a single local oscillator (LO), and the RF receiver is configured to filter a received signal using a complex filter having a variable center frequency. In accordance with another aspect, many RF receivers are combined to form an aggregate carrier receiver.

Abstract: A switched mode power supply comprises a control signal generator arranged to generate first and second control signals via first and second outputs, respectively, which are coupled to respective first and second inputs of a switching stage, by means of respective first and second control signal paths. The switching stage is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element by coupling it alternately to first and second supply voltages. An adjustable delay stage in one of the first and second signal paths is arranged to control an adjustable delay so that a first delay experienced by the first control signal passing from the control signal generator's first output to the switching stage's first input is substantially equal to a second delay experienced by the second control signal passing from the control signal generator's second output to the switching stage's second input.

Abstract: A Radio Frequency (RF) receiver is provided. The RF receiver is configured to simultaneously receive at least two radio frequency bands with a single receiver path. The RF receiver comprises a single local oscillator (LO), and the RF receiver is configured to filter a received signal using a complex filter having a variable center frequency. in accordance with another aspect, many RF receivers are combined to form an aggregate carrier receiver.

Abstract: A switched mode power supply comprises a control signal generator arranged to generate first and second control signals via first and second outputs, respectively, which are coupled to respective first and second inputs of a switching stage, by means of respective first and second control signal paths. The switching stage is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element by coupling it alternately to first and second supply voltages. An adjustable delay stage in one of the first and second signal paths is arranged to control an adjustable delay so that a first delay experienced by the first control signal passing from the control signal generator's first output to the switching stage's first input is substantially equal to a second delay experienced by the second control signal passing from the control signal generator's second output to the switching stage's second input.

Abstract: A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

Abstract: An electrical circuit can have a local oscillator, a first mixer, a second mixer, and a delay element. The first mixer mixes an input signal with a local oscillator signal. The second mixer mixes the input signal with a delayed local oscillator signal, delayed by the delay element. The output signals from the first mixers are combined to form an output signal of the electrical circuit.

Abstract: A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

Abstract: A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

Abstract: A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

Abstract: A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

Abstract: A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.

Abstract: A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

Abstract: A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.

Abstract: A switched mode power supply comprises a control signal generator arranged to generate first and second control signals via first and second outputs, respectively, which are coupled to respective first and second inputs of a switching stage, by means of respective first and second control signal paths. The switching stage is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element by coupling it alternately to first and second supply voltages. An adjustable delay stage in one of the first and second signal paths is arranged to control an adjustable delay so that a first delay experienced by the first control signal passing from the control signal generator's first output to the switching stage's first input is substantially equal to a second delay experienced by the second control signal passing from the control signal generator's second output to the switching stage's second input.

Abstract: A switched mode power supply (100) comprises a reactive element (10) and a control signal generator (30) is arranged to generate a first control signal at a first output (31) of the control signal generator (30) and a second control signal at a second output (32) of the control signal generator (30). The first output (31) of the control signal generator (30) is coupled to a first input (21) of a switching stage (20) by means of a first control signal path (40) and the second output (32) of the control signal generator (30) is coupled to a second input (22) of the switching stage (20) by means of a second control signal path (50). The switching stage (20) is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element (10) by coupling it alternately to first and second supply voltages.

Abstract: A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.

Abstract: A receiver for a three-wire digital interface, a method for operating a three-wire digital interface, a signalling system comprising the receiver, and a wireless communication device comprising the signalling system. The receiver for a three-wire digital interface comprises a first resistive element coupled between a first input terminal and a first junction node, a second resistive element coupled between a second input terminal and a second junction node, and a third resistive element coupled between a third input terminal and a third junction node. A network comprising first second and third network terminals is coupled to first, second and third junction nodes. The network has substantially the same impedance between all pairs of the first, second and third network terminals.

Abstract: A switched mode power supply (100) comprises a reactive element (10) and a control signal generator (30) is arranged to generate a first control signal at a first output (31) of the control signal generator (30) and a second control signal at a second output (32) of the control signal generator (30). The first output (31) of the control signal generator (30) is coupled to a first input (21) of a switching stage (20) by means of a first control signal path (40) and the second output (32) of the control signal generator (30) is coupled to a second input (22) of the switching stage (20) by means of a second control signal path (50). The switching stage (20) is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element (10) by coupling it alternately to first and second supply voltages.

Abstract: A receiver (100) for a three-wire digital interface, comprises a first resistive element (R1) coupled between a first input terminal (A) and a first junction node (JA), a second resistive element (R2) coupled between a second input terminal (B) and a second junction node (JB), and a third resistive element (R3) coupled between a third input terminal (C) and a third junction node (JC). A network (70) comprising first second and third network terminals (71, 72, 73) is coupled to, respectively, first, second and third junction nodes (JA, JB, JC). The network has substantially the same impedance between all pairs of the first, second and third network terminals. A first comparator (C1) has a non-inverting input (10) coupled to the first input terminal (A), an inverting input (12) coupled to the second junction node (JB), and an output (14) coupled to a first output terminal (AJ).

Abstract: A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.