Abstract: A signal filter (100) comprises a first transferred impedance filter, TIF, (TIFA) having four differential signal paths (PA,1, PA,2, PA,3, PA,4) and a second TIF (TIFB) having four differential signal paths (PB,1, PB,2, PB,3, PB,4)- A first differential signal port of the first TIF (32A) is coupled to a first differential signal port of the second TIF (32B). A first clock generator (12A) is arranged to provide first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I?, CLKA,Q?) having four non-overlapping phases for selecting the respective first-TIF differential signal paths (PA,1, PA,2, PA,3, PA,4), and a second clock generator (12B) is arranged to provide second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,J?, CLKB,Q?) having four non-overlapping phases for selecting the respective second-TIF differential signal paths (PB,1, PB,2, PB,3, PB,4).

Abstract: A continuous-time MASH sigma-delta analogue-to-digital converter ADC. The ADC may include first and second modulators and an output stage. The ADC may be provided with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract: A signal filter (100) comprises a first transferred impedance filter, TIF, (TIFA) having four differential signal paths (PA,1, PA,2, PA,3, PA,4) and a second TIF (TIFB) having four differential signal paths (PB,1, PB,2, PB,3, PB,4)?. A first differential signal port of the first TIF (32A) is coupled to a first differential signal port of the second TIF (32B). A first clock generator (12A) is arranged to provide first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I?, CLKA,Q?) having four non-overlapping phases for selecting the respective first-TIF differential signal paths (PA,1, PA,2, PA,3, PA,4), and a second clock generator (12B) is arranged to provide second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,J?, CLKB,Q?) having four non-overlapping phases for selecting the respective second-TIF differential signal paths (PB,1, PB,2, PB,3, PB,4).

Abstract: Continuous-time MASH sigma-delta ADC with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract: An analogue to digital converter uses charge sampling in combination with a successive approximation conversion technique in order to combine anti-alias filtering and quadrature downconversion functions into the data converter. The conversion method is an energy-efficient realization for wide-band radio systems with moderate resolution specifications such as 4G or ultra-wideband radio (UWB). The converter uses two capacitor matrices, one to perform charge sampling, and one to be used simultaneously in the successive approximation technique, so that full use of an input signal is made and efficiency is maximized.

Abstract: Various embodiments are disclosed relating to techniques of filtering and down-converting a received signal. In accordance with an example embodiment of the present invention, an analog signal may be received and amplified in a transconductance amplifier. The amplified signal may be connected to a switching arrangement and an impedance circuit connected in series, and frequency down-converted in a second circuit. The resulting analog base band signal may be fed back to a base band input between the switching arrangement and the impedance circuit.

Abstract: The invention relates to an electronic circuit and a method capable of providing feedback in the electronic circuit, such that the effect of leakage currents in the circuit are minimised. The method includes the steps of storing an analogue input signal using an analogue storage device, converting the stored analogue input signal into a digital signal and storing the digital signal, converting the stored digital signal into an analogue feedback signal, and providing feedback in the electronic circuit using the analogue feedback signal.

Abstract: An analogue to digital converter uses charge sampling in combination with a successive approximation conversion technique in order to combine anti-alias filtering and quadrature downconversion functions into the data converter. The conversion method is an energy-efficient realization for wide-band radio systems with moderate resolution specifications such as 4G or ultra-wideband radio (UWB). The converter uses two capacitor matrices, one to perform charge sampling, and one to be used simultaneously in the successive approximation technique, so that full use of an input signal is made and efficiency is maximised.

Abstract: An apparatus, having as an input an analog signal, is provided. The apparatus comprises a first circuit comprising an impedance transferring circuit configured to band pass filter the input signal, obtaining a filtered signal; the impedance transferring circuit comprising: a transconductance amplifier (1102), and a switching arrangement (1106, 1108) and an impedance circuit (404) connected in series, the switching arrangement being configured to switch the impedance of the impedance circuit of the impedance transferring circuit from base band to the frequency of the input signal. The apparatus further comprises a second circuit (1112) configured to perform down mixing to the filtered signal obtaining a base band signal and a feedback loop connecting the base band signal to the switching arrangement (1114, 1116) and the impedance circuit, the signal of the feedback loop configured to control the properties of the first circuit.

Abstract: A delta-sigma A/D converter includes a D/A converter realized with a mixed-mode comb filter connected in a feedback loop from the output of the A/D converter to the input of the A/D converter. The D/A converter is configured to predistort a feedback signal. The converter further includes an analogue filter at the input of the A/D converter. The analogue filter is configured to cancel the predistortion of the feedback signal.

Abstract: A delta-sigma A/D converter includes a D/A converter realized with a mixed-mode comb filter connected in a feedback loop from the output of the A/D converter to the input of the A/D converter. The D/A converter is configured to predistort a feedback signal. The converter further includes an analogue filter at the input of the A/D converter. The analogue filter is configured to cancel the predistortion of the feedback signal.

Abstract: The invention relates to an electronic device and a method of enhancing character input in an electronic device comprising a set of keys. The method comprises associating a group of characters with at least one key; detecting repeated presses of a key; detecting whether the key has been touched continuously during the repeated presses of the key; and interpreting the characters corresponding to the key presses in the group of characters associated with the key on the basis of the detections.

Abstract: An energy-efficient acceleration measurement system is presented. The system includes an accelerometer, responsive to acceleration of the system, for providing an accelerometer output signal having a magnitude indicative of at least one component of the acceleration. A motion detector is responsive to the accelerometer output signal, and provides a processor interrupt signal, but only if the magnitude of acceleration reaches a threshold. The processor, responsive to the processor interrupt signal, measures the acceleration with higher accuracy than the motion detector is capable of, but in a way that consumes more power than was needed by the motion detector.

Abstract: The invention relates to an electronic device and a method of enhancing character input in an electronic device comprising a set of keys. The method comprises associating a group of characters with at least one key; detecting repeated presses of a key; detecting whether the key has been touched continuously during the repeated presses of the key; and interpreting the characters corresponding to the key presses in the group of characters associated with the key on the basis of the detections.

Abstract: An energy-efficient acceleration measurement system is presented. The system includes an accelerometer, responsive to acceleration of the system, for providing an accelerometer output signal having a magnitude indicative of at least one component of the acceleration. A motion detector is responsive to the accelerometer output signal, and provides a processor interrupt signal, but only if the magnitude of acceleration reaches a threshold. The processor, responsive to the processor interrupt signal, measures the acceleration with higher accuracy than the motion detector is capable of, but in a way that consumes more power than was needed by the motion detector.