Abstract: A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

Abstract: A method of producing a ferroelectric capacitor includes forming a first insulating layer on a semiconductor substrate with an MOSFET. After a first interlayer insulating layer is formed, a first conductive layer, a ferroelectric layer, and a second conductive layer are laminated on the first interlayer insulating layer to form a ferroelectric capacitor. After a first opening is formed in a ferroelectric thin layer, first restoration annealing is performed relative to a first member formed of a first interlayer insulating layer and the ferroelectric capacitor. A second interlayer insulating layer is formed on the first interlayer insulating layer, and a second opening is formed in the second interlayer insulating layer through etching. Then, second restoration annealing is performed relative to a second member formed of the first member and the second interlayer insulating layer with the second opening under in an order of nitrogen, oxygen, and nitrogen, respectively.

Abstract: A semiconductor substrate formed with a MOSFET is prepared, and a first interlayer insulating film is deposited on the semiconductor substrate. A ferroelectric capacitor is formed on the first interlayer insulating film. Next, a second interlayer insulating film is formed on a first structure provided with the semiconductor substrate, the first interlayer insulating film and the ferroelectric capacitor so as to embed the ferroelectric capacitor therein. Openings for electrically connecting the MOSFET and the ferroelectric capacitor and an external circuit of a ferroelectric memory are formed in the second interlayer insulating film to form a second structure. A metal wiring is formed on the second interlayer insulating film to form a third structure. Next, the third structure is heat-treated in an atmosphere from over 350° C. to under 450° C.

Abstract: A thin-film capacitor includes a lower electrode film, a high dielectric film and an upper electrode film disposed sequentially. One film of the three films includes first and second edge portions placed opposite to each other. Furthermore, the one film includes a first opening which extends from the first edge portion toward the second edge portion and a second opening which extends from the second edge portion toward the first edge portion. Also, the first and second openings are respectively terminated away from the second and first edge portions. Alternatively, one film of the three films includes a plurality of edge portions which configure an outline of the one film. Furthermore, the one film includes a plurality of openings which respectively extend therethrough and which are terminated away from all the edge portions. Also, there is provided a manufacturing method of the thin-film capacitor.

Abstract: A semiconductor memory device includes a plate line driving portion having a control transistor connected to a plate line, a selection transistor in which a control electrode is connected to a word line and one end of a main current path is connected to a bit line, a ferroelectric capacitor connected to the other end of the main path of the selection transistor and the plate line, a first power supply connected to a sense amplifier and a precharge circuit, and a second power supply connected to a plate line driving portion, disposed as a separate system from the first power supply and insulated at the time of non-operation from the first power supply. The selection transistor is formed in a first semiconductor region and a main current path of the control transistor is formed in a second semiconductor region that is insulated through insulating films from the first region.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n?1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read, out from each dummy memory cell, a potential Va is developed on a bit line BL2n?1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n?1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn?1 and SAn as a reference potential.

Abstract: A semiconductor memory device includes a plate line driving portion having a control transistor connected to a plate line, a selection transistor in which a control electrode is connected to a word line and one end of a main current path is connected to a bit line, a ferroelectric capacitor connected to the other end of the main path of the selection transistor and the plate line, a first power supply connected to a sense amplifier and a precharge circuit, and a second power supply connected to a plate line driving portion, disposed as a separate system from the first power supply and insulated at the time of non-operation from the first power supply. The selection transistor is formed in a first semiconductor region and a main current path of the control transistor is formed in a second semiconductor region that is insulated through insulating films from the first region.

Abstract: A semiconductor memory device includes a plate line driving portion having a control transistor connected to a plate line, a selection transistor in which a control electrode is connected to a word line and one end of a main current path is connected to a bit line, a ferroelectric capacitor connected to the other end of the main path of the selection transistor and the plate line, a first power supply connected to a sense amplifier and a precharge circuit, and a second power supply connected to a plate line driving portion, disposed as a separate system from the first power supply and insulated at the time of non-operation from the first power supply. The selection transistor is formed in a first semiconductor region and a main current path of the control transistor is formed in a second semiconductor region that is insulated through insulating films from the first region.

Abstract: A ferroelectric memory reads data from a memory cell by using a sense amplifier to compare a reference potential with a potential produced on a bit line by the memory cell. The reference potential may generated by a pre-charge circuit connected to the sense amplifier. Alternatively, the reference potential may be generated by the memory cell itself. In either case, the reference potential is obtained without the need for a reference cell, and without the need to drive a bit line to the reference potential. Current consumption is accordingly reduced, and integration density can be increased.

Abstract: A semiconductor memory includes bit lines, memory cells and a sense amplifier both of which are connected to the bit lines. Each of the memory cells includes a transistor and a capacitor. The capacitor is made of a material having a quantity of residual dielectric polarization in an electroless state in a hysteresis characteristic that is not reduced to less than a threshold value until after a lapse of a time of a refreshing cycle. The refresh cycle includes clock cycles. The sense amplifier detects an output current on the bit lines due to the residual dielectric polarization. The sense amplifier amplifies the output current to refresh the quantity of residual dielectric polarization of the capacitor when the detected level is equal to or larger than the threshold value. The sense amplifier does not amplify the output current when the detected level is less than the threshold value.

Abstract: A semiconductor memory includes bit lines, memory cells and a sense amplifier both of which are connected to the bit lines. Each of the memory cells includes a transistor and a capacitor. The capacitor is made of a material having a quantity of residual dielectric polarization in an electroless state in a hysteresis characteristic that is not reduced to less than a threshold value until after a lapse of a time of a refreshing cycle. The refresh cycle includes clock cycles. The sense amplifier detects an output current on the bit lines due to the residual dielectric polarization. The sense amplifier amplifies the output current to refresh the quantity of residual dielectric polarization of the capacitor when the detected level is equal to or larger than the threshold value. The sense amplifier does not amplify the output current when the detected level is less than the threshold value.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n−1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read, out from each dummy memory cell, a potential Va is developed on a bit line BL2n−1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n−1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn−1 and SAn as a reference potential.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n−1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read out from each dummy memory cell, a potential Va is developed on a bit line BL2n−1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n−1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn−1 and SAn as a reference potential.

Abstract: For the purpose of converting ferroelectric memory between (use as) RAM and ROM, a method of manufacturing a read-only memory (ROM) using a ferroelectric memory is realized by a chip assembly process to perform chip assembly for ferroelectric memory; a data writing process to write data to the ferroelectric memory after the chip assembly process; and a first heat treatment process to subject the ferroelectric film of ferroelectric memory, after the data writing process, to a heat treatment at a heat treatment temperature T1 (° C.) lower than the phase transition temperature Tc (° C.) of the ferroelectric film.

Abstract: A ferroelectric memory of the present invention comprises a memory cell which includes a select transistor whose control electrode, first electrode and second electrode are respectively connected to a word line, a bit line and a first node, a ferroelectric capacitor whose first electrode and second electrode are respectively connected to the first node and connected to a plate line through a second node, and a resistor connected between the first node and the second node.

Abstract: A ferroelectric memory reads data from a memory cell by using a sense amplifier to compare a reference potential with a potential produced on a bit line by the memory cell. The reference potential may generated by a pre-charge circuit connected to the sense amplifier. Alternatively, the reference potential may be generated by the memory cell itself. In either case, the reference potential is obtained without the need for a reference cell, and without the need to drive a bit line to the reference potential. Current consumption is accordingly reduced, and integration density can be increased.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n−1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read out from each dummy memory cell, a potential Va is developed on a bit line BL2n−1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n−1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn−1 and SAn as a reference potential.

Abstract: A ferroelectric memory device in which an imprint is prevented, and a method of operating the ferroelectric memory device to prevent its characteristics from deteriorating due to an imprint. The ferroelectric memory device includes a sense amplifier having first and second transistors which connect first and third sub-bit lines to a ground in accordance with a sense amplifier control signal, third and fourth transistors which connect the first sub-bit line with a fourth sub-bit line and further connect the third sub-bit line with a second sub-bit line in accordance with a first switching control signal, and fifth and sixth transistors which connect the first sub-bit line with the second sub-bit line and further connect the third sub-bit line with the fourth sub-bit line in accordance with a second switching control signal.

Abstract: A ferroelectric memory of the present invention comprises a memory cell which includes a select transistor whose control electrode, first electrode and second electrode are respectively connected to a word line, a bit line and a first node, a ferroelectric capacitor whose first electrode and second electrode are respectively connected to the first node and connected to a plate line through a second node, and a resistor connected between the first node and the second node.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n−1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read out from each dummy memory cell, a potential Va is developed on a bit line BL2n−1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n−1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn−1 and SAn as a reference potential.