Abstract: A superfine multi-core Nb3Al superconductive wire is produced by getting a Nb3Al superconductive wire ready which was obtained by subjecting a precursor wire having a superfine multi-core structure in which a plurality of Nb/Al complex cores are embedded in Nb, Ta, a Nb based dilute alloy, or a Ta based dilute alloy as the matrix to a rapid heating and quenching treatment comprising rapidly heating to a temperature range near 2,000° C. in 2 seconds, (A) coating the Nb3Al superconductive wire with Cu or Ag as the stabilizing material; then (B) subjecting to a hot isostatic press (HIP) process for 10 minutes or more in a inert gas environment with a pressure of 40 atmospheres or more; and then (C) subjecting heat treatment for 1-200 hours in temperature range of 680-850° C.

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cell to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: A method of operating an electrically alterable non-volatile multi-level memory device includes settling a status of at least one of the memory cell to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: An image forming apparatus includes: a communications interface operative to receive a first image information item transmitted from terminal equipment connected thereto via a network; a storage section operative to store the first image information item therein; and an image reading section operative to obtain a second image information item by scanning an image of a document. The image forming apparatus further includes: a control section operative to compare the second image information item to the first image information item and then select the first image information item to be served for image forming if the second image information item is judged to be same as the first image information item, or the second image information item to be served for image forming if the second image information item is judged to be different from the first image information item.

Abstract: Phosphors for a display, which emit blue light and green light, comprise zinc sulfide phosphors having a crystal structure of a hexagonal system. The zinc sulfide phosphor which emits blue light has an average particle diameter in a range of (0.0169×VE1.9+2.49)±20%[?m] when an electron beam has an acceleration voltage VE. The zinc sulfide phosphor which emits green light has an average particle diameter in a range of (0.017×VE1.9+2.58)±20%[?m]. A phosphor for a display, which emits red light, comprises a yttrium oxysulfide phosphor or a yttrium oxide phosphor and has an average particle diameter in a range of (0.023×VE1.95+2.88)±20%[?m]. These phosphors for a display are used for a display which has an electron beam having an acceleration voltage of 3 kV to 15 kV as an excitation source.

Abstract: A sheet transport apparatus of the present invention is arranged so that a first eject tray is located at a position to which sheets are ejectable in such a manner that front and back surfaces of the sheets are not reversed after the sheets are subjected to predetermined processing. Further, the sheet transport apparatus of the present invention is provided with a first eject tray operation section for aligning leading edges of the sheets ejected to the first eject tray by changing a positional relation in a vertical direction between an upstream side and a downstream side of the first eject tray in a sheet transporting direction.

Abstract: By rapidly heating a precursor wire having a multifilamentary structure in which multiple composite cores in which a composite compound of an Nb—Ga compound and Nb is embedded in Nb are embedded in Nb, Ta, Nb-base alloy or Ta-base alloy as a matrix material to a temperature range of 1400 to 2100° C. in 2 seconds, quenching the precursor wire at a rate of 5000° C./second or larger, and subjecting the precursor wire to additional heat treatment at a temperature range of 600 to 850° C. for 1 to 400 hours, a superconducting wire having a multifilamentary structure in which multiple composite cores in which a composite compound containing Nb3Ga of a stoichiometric composition embedded in Nb are embedded in Nb, Ta, Nb-base alloy or Ta-base alloy as a matrix material is obtained.

Abstract: A method of operating an electrically alterable non-volatile multi-level memory device includes settling a status of at least one of the memory cell to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: A apparatus and method for manufacturing a laminated optical disc that include an adhesive applying device adapted to apply an adhesive to a first substrate, and forming an adhesive layer having a specific thickness between the first substrate and a second substrate superimposed onto the first substrate. The manufacturing apparatus and method may further include a provisional bonding device adapted to partially cure the adhesive layer to partially bond and provisionally fasten the first substrate and the second substrate.

Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.

Abstract: A apparatus and method for manufacturing a laminated optical disc that include an adhesive applying device adapted to apply an adhesive to a first substrate, forming an adhesive layer having a specific thickness between the first substrate and a second substrate superimposed onto the first substrate. The manufacturing apparatus and method further include an adhesive supply source adapted to supply the adhesive to the adhesive applying device at a first predetermined temperature and a defoaming tank adapted to remove bubbles from the adhesive at a second predetermined temperature, which is higher than the first predetermined temperature.

Abstract: A apparatus and method for manufacturing a laminated optical disc that include an adhesive applying device adapted to apply an adhesive to a first substrate, forming an adhesive layer having a specific thickness between the first substrate and a second substrate superimposed onto the first substrate, and a suction device adapted to suction the adhesive layer formed between the first substrate and the second substrate with a predetermined suction force. The manufacturing apparatus and method may further include a provisional bonding device adapted to partially cure the suctioned adhesive layer to partially bond and provisionally fasten the first substrate and the second substrate.

Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: By rapidly heating a precursor wire having a multifilamentary structure in which multiple composite cores in which a composite compound of an Nb—Ga compound and Nb is embedded in Nb are embedded in Nb, Ta, Nb-base alloy or Tabase alloy as a matrix material to a temperature range of 1400 to 2100° C. in 2 seconds, quenching the precursor wire at a rate of 5000° C./second or larger, and subjecting the precursor wire to additional heat treatment at a temperature range of 600 to 850° C. for 1 to 400 hours, a superconducting wire having a multifilamentary structure in which multiple composite cores in which a composite compound containing Nb3Ga of a stoichiometric composition embedded in Nb are embedded in Nb, Ta, Nb-base alloy or Tabase alloy as a matrix material is obtained.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: A circuit verification apparatus, a circuit verification program and a circuit verification method are provided in which in the verification of a circuit according to software, the probability that an accumulation circuit such as a queue circuit, etc., changes into a saturated state can be increased without changing the logic of the circuit to be verified, thus making it possible to shorten the time required for the circuit verification.

Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.

Abstract: Engine oil compositions are provided containing (A) a lubricating base oil having a kinematic viscosity at 100° C. of 3 to 6 mm2/S, a viscosity index of 120 or more, and a total aromatic content of 5 percent by mass or less and (B) a polymethacrylate-based viscosity index improver, preferably having a weight average molecular weight of 180,000 or more, (A) and (B) being blended in such an amount that the composition has a kinematic viscosity at 100° C. of 4.0 to 9.3 mm2/s. The engine oil compositions may also contain a molybdenumdithiocarbamate, as well as one or more other engine oil additives. The engine oil compositions preferably have a high-temperature, high shear viscosity at 150° C. of 2.4 to 2.7 mPa·s, a NOACK evaporation loss of 16 percent by mass or less, and a CCS viscosity at −25° C. of 3500 mPa·s or less.

Abstract: A power supply device 3 including: a current source 31 for supplying current to a load circuit 4 which operates on the supplied current, and a power switch unit 32 between the current source 31 and the load circuit 4 to control passage of current, wherein: the power switch unit 32 includes a switching element 323 connected in parallel with the open-close element 321, a power supply controller 33 including an open-close element controller 31 which controls operation of the open-close element 321 and a switching element controller 332 which controls operation of the switching element 323, and a voltage detector 34 which detects terminal voltage of the load circuit 4; and the power switch unit 32 turns on the switching element before supplying current to the load circuit and closes the open-close element when the terminal voltage of the load circuit becomes almost equal to supply voltage.