Patents by Inventor Kiyoshi Kuwabara
Kiyoshi Kuwabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9455241Abstract: Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.Type: GrantFiled: June 29, 2015Date of Patent: September 27, 2016Assignee: STMICROELECTRONICS PTE LTDInventors: Yonggang Jin, Kiyoshi Kuwabara, Xavier Baraton
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Publication number: 20150303168Abstract: Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.Type: ApplicationFiled: June 29, 2015Publication date: October 22, 2015Inventors: YONGGANG JIN, KIYOSHI KUWABARA, XAVIER BARATON
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Publication number: 20100187651Abstract: Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.Type: ApplicationFiled: October 13, 2009Publication date: July 29, 2010Applicant: STMicroelectronics Asia Pacific Pte Ltd.Inventors: Yonggang JIN, Kiyoshi Kuwabara, Xavier Baraton
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Patent number: 6706546Abstract: A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.Type: GrantFiled: January 8, 2001Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Kiyoshi Kuwabara, Solomon I. Beilin, Michael Peters, Wen-Chou Vincent Wang, Masaaki Inao
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Publication number: 20020039464Abstract: A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.Type: ApplicationFiled: January 8, 2001Publication date: April 4, 2002Inventors: Tetsuzo Yoshimura, Yasuhito Takahashi, Kiyoshi Kuwabara, Solomon I. Beilin, Michael Peters, Wen-chou Vincent Wang, Masaaki Inao
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Patent number: 5667401Abstract: A cable connector includes cables, and jacks attached to ends of the cables. The jacks have contacts connected to the cables. The contacts extend in a first direction substantially perpendicular to a second direction in which the cables extend from the jacks.Type: GrantFiled: May 31, 1995Date of Patent: September 16, 1997Assignee: Fujitsu LimitedInventors: Kiyoshi Kuwabara, Tetsuro Yamada, Takeshi Nishiyama, Masahiko Sakuraoka
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Patent number: 5437558Abstract: A connector comprising a plug member having pin-like male contacts and a jack member having female contacts, the jack member being coupled with the plug member by a plug-in connection. A skirt having a plurality of holes is arranged to hold the pin-like male contacts in position. The skirt is supported in the plug member by the locating groove-pin engagement. The locating groove-pin engagement is released by the jack member when the jack member is inserted into the plug member and reestablished by the jack member when the jack member is withdrawn from the plug member. The skirt also has an alignment pin which is received in a locating hole of the jack member when the jack member is inserted into the plug member. Therefore, it is possible to insert the jack member in the plug member without the pin-like male contacts being bent, as well as to easily withdraw the jack member from the plug member.Type: GrantFiled: August 20, 1993Date of Patent: August 1, 1995Assignee: Fujitsu LimitedInventors: Masahiko Sakuraoka, Kouichi Hara, Kiyoshi Kuwabara, Misao Umematsu
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Patent number: 5181317Abstract: A method of making an engineering change to a printed wiring board changes connection for a terminal of an electronic component which is mounted on the printed wiring board through a terminal pad. The terminal is electrically connected to a destination through the terminal pad and wiring within the printed wiring board. The present invention places an insulator, including an insulating material and a conductive layer formed thereon, between the terminal and the terminal pad. The electronic component is mounted on the printed wiring board and the terminal is electrically connected to the conductive layer. A discrete wire is placed between the conductive layer and the destination.Type: GrantFiled: September 27, 1991Date of Patent: January 26, 1993Assignee: Fujitsu LimitedInventors: Mikio Nishihara, Teruo Murase, Kiyotaka Seyama, Kiyoshi Kuwabara, Osamu Ohshima
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Patent number: 4785141Abstract: A wiring structure for a termination circuit in which a termination circuit is connected to an integrated circuit through a fixed wiring pattern provided in a leadout layer closest to the mounting surface.Type: GrantFiled: November 18, 1987Date of Patent: November 15, 1988Assignee: Fujitsu LimitedInventors: Mikio Nishihara, Kiyoshi Kuwabara
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Patent number: 4692843Abstract: A multilayer printed wiring board having an air gap between neighboring printed wiring boards of the multilayer printed wiring board by inserting plated spacers to both end faces of through-hole pads which are provided to each printed wiring board so that each through-hole pad opposes to another through-hole pad on the neighboring printed wiring board. The spacers opposed to each other are joined together by solder, and each spacer has an end surface having a size being smaller than a size of the end surface of each through-hole pad to provide a drop part at the joint part of the spacers, so that melted solder stays at the drop part not flowing toward the board through the side surface of the through-hole pad when the printed wiring boards are integrated to the multilayer printed wiring board under pressure and high temperature.Type: GrantFiled: November 13, 1986Date of Patent: September 8, 1987Assignee: Fujitsu LimitedInventors: Masaru Matsumoto, Mikio Nishihara, Kiyoshi Kuwabara
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Patent number: 4675789Abstract: A high density multilayer printed circuit board comprising generally parallel signal layers, electric source layers, and ground layers, with insulating layers arranged between the signal layers and the electric source layers, between the electric source layers and the ground layers, and between the ground layers and the signal layers respectively. Conductor portions are formed in through holes which are opened in a direction transverse to the signal layers, electric source layers, and ground layers. The conductor portions are electrically connected to the signal layers and/or the electric source layers, and/or the ground layers, through the lands thereof, the connections of the lands being substantially equally distributed among the conductor portions.Type: GrantFiled: December 20, 1985Date of Patent: June 23, 1987Assignee: Fujitsu LimitedInventors: Kiyoshi Kuwabara, Mikio Nishihara, Kazuhisa Tsunoi