INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.
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This application claims the benefit of U.S. Provisional Patent Application No. 61/147,430, filed on Jan. 26, 2009, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit.
2. Discussion of the Related Art
With continuously decreasing semiconductor device dimensions and increasing device packaging densities, the packaging of semiconductor devices has continued to gain in importance. In the electronics industry, the continuing goal has been to reduce the size of electronic devices such as in digital cameras and camcorders. Metal interconnects, thereby including points of metal contact solder bumps that connect a semiconductor to surrounding circuits, increasingly become important.
SUMMARY OF THE INVENTIONAccordingly, the present invention is directed to an integrated circuit package and method of forming the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An advantage of an embodiment of the invention is to provide reduced processing steps for foaming a chip packing.
Another advantage of an embodiment of the invention is to provide a reduced cost of forming a chip packing.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, an embodiment of the invention is directed towards an integrated circuit package. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.
In another aspect, an embodiment of the invention is directed towards a method of forming an integrated circuit package. The method includes forming a lead frame including a first portion and a second portion. The first portion and the second portion of the lead frame intersect at an angle ranging from about 45 degrees to about 135 degrees. An adhesive material is formed on the first portion of the lead frame and a carrier is attached to the lead frame with the adhesive material. An integrated circuit is also attached to the adhesive material. Interconnects are formed on the integrated circuit and protective material is formed on the integrated circuit.
In another aspect, an embodiment of the invention is directed towards a method of making an integrated circuit package. The method includes forming a lead frame including a first portion and a second portion. The first portion and the second portion of the lead frame intersect at an angle ranging from about 45 degrees to about 135 degrees. A double sided thermal tape is adhered to a bottom surface of the first portion of the lead frame; attaching a carrier to the lead frame with the thermal double-sided thermal tape is also part of the method. The method further includes attaching an integrated circuit to the thermal double-sided adhesive tape adjacent to the first portion of the lead frame and forming at least one pillar interconnect on the integrated circuit. A compressive compound is formed over the integrated circuit as well as over the first and second portions of the lead frame. The compressive compound is hardened by heating the compressive compound to a temperature in the range of about 120° C. to about 150° C.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
In the drawings:
Reference will now be made in detail to an embodiment of the present invention, an example of which is illustrated in the accompanying drawings.
Referring to
An integrated circuit chip 206 is attached to the adhesive material 202. The integrated circuit chip 206 is arranged between second portions 104 of the lead frame 100. At least one interconnect 208 is formed on the integrated circuit chip 206. In a preferred embodiment, the interconnect 208 includes a conductive material, e.g., copper, gold, pewter, combinations thereof, and the like, formed by plating as known in the art. In a preferred embodiment, the interconnect is a copper pillar bump. Of course, other conductive materials may also be used, such as alloys and the like.
Referring to
In a preferred embodiment, the hardening process includes heating the compound to a temperature ranging from about 120° C. to about 150° C. for a time ranging from about 2 to about 10 minutes. Also, in the preferred embodiment, the epoxy part is R4212 epoxy molding compound from Nagase Corp. of Japan.
Referring to
Referring to
Referring to
A first passivation layer 606 is formed on the interconnect traces 602 and a second passivation layer 608 is formed on the interconnect traces 604. The first passivation layer 606 is etched to form a contact hole 610. The first and second passivation layers are formed of insulative material via polymers, e.g., photosensitive liquid polymers. The insulating materials may include parylene, polyimide, benzocyclobutene (BCB), polybenzoxazole. (PBO), combinations thereof, and the like. The first and second passivation layers may be formed of different materials. A solder ball 612 is formed in the contact hole 610. The solder ball 612 is formed from conventional processes and may include a conductive material, such as silver, copper, tin, combinations thereof, and the like. Components 614, such as passive or active components including, for example, capacitors, resistors, transistors, inductors, combinations thereof, and the like, are attached to the interconnect traces 604.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims
1. An integrated circuit package, comprising:
- an integrated circuit;
- a protective material on at least a portion of the integrated circuit;
- a lead frame coupled to the integrated circuit;
- a conductive layer coupled to the interconnect;
- a solder ball coupled the conductive layer; and
- a passivation layer on the conductive layer.
2. The integrated circuit package of claim 1, wherein the protective material comprises a compressive molding compound.
3. The integrated circuit package of claim 2, wherein the compressive molding compound comprises epoxy.
4. The integrated circuit package of claim 1, wherein the lead frame comprises a material selected from the group consisting of Al, Au, Cu, and combinations thereof.
5. The integrated circuit package of claim 1, wherein the passivation layer comprises an insulating polymer selected from the group consisting of parylene, polyimide, benzocyclobutene (BCB), and polybenzoxazole (PBO).
6. The integrated circuit package of claim 1, wherein the lead frame comprises a conductive material selected from the group consisting of Au, Al, Cu, Ti, and alloys of the same.
7. The integrated circuit package of claim 1, further comprising at least one of active and passive components electrically coupled to the integrated circuit.
8. A method of forming an integrated circuit package, comprising the steps of:
- forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from about 45 degrees to about 135 degrees;
- forming an adhesive material on the first portion of the lead frame;
- attaching a carrier to the lead frame with the adhesive material;
- attaching an integrated circuit to the adhesive material;
- forming an interconnect on the integrated circuit; and
- forming a protective material on the integrated circuit.
9. The method of claim 8, wherein the angle is in the range from about 85 degrees to about 95 degrees.
10. The method of claim 8, wherein forming the protective layer comprises the step of:
- heating an epoxy material to a temperature in the range from about 120° C. to about 150° C. to harden the epoxy material.
11. The method of claim 8, further comprising removing the carrier and the adhesive material by heating an epoxy material to a temperature from about 175° C. to about 260° C. to thermally release the adhesive material and carrier.
12. The method of claim 11, further comprising the steps:
- removing a portion of the hardened epoxy material to expose the interconnect and the first portion of the lead frame; and
- removing the second portion of the lead frame.
13. The method of claim 12, wherein removing the portion of hardened epoxy material comprises grinding an upper surface of the hardened compound.
14. The method of claim 12, further comprising the steps of:
- forming a conductive material on the hardened compound;
- forming a passivation layer on the conductive material; and
- faulting a solder ball on the passivation layer, wherein the solder ball is electrically coupled to the conductive material.
15. A method of making an integrated circuit package, comprising the steps of:
- forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from about 45 degrees to about 135 degrees;
- adhering a double-sided thermal tape to a bottom surface of the first portion of the lead frame;
- attaching a carrier to the lead frame with the double-sided thermal tape;
- attaching an integrated circuit to the double-sided thermal adhesive tape adjacent to the first portion of the lead frame;
- forming at least one pillar interconnect on the integrated circuit;
- forming a compressive compound over the integrated circuit and the first and second portions of the lead frame; and
- hardening the compressive compound by heating the compressive compound to a temperature in the range from about 120° C. to about 150° C.
16. The method of claim 15, further comprising the steps:
- removing a portion of the hardened molding to expose the pillar interconnect and the second portion of the lead frame; and
- removing the first portion of the lead frame.
17. The method of claim 16, wherein the removing the portion of compressive molding step comprises grinding an upper surface of the compressive molding.
18. The method of claim 17, further comprising the steps of:
- forming a conductive material on the hardened molding;
- forming a first passivation layer on an upper surface of the conductive material;
- forming a second passivation layer on a lower surface of the compressive molding material; and
- forming a solder ball on the first passivation layer, wherein the solder ball is electrically coupled to the conductive material.
19. The method of claim 15, wherein the compressive molding material comprises an epoxy material.
20. The method of claim 18, further comprising the steps of attaching a component to the lower surface of the compressive molding.
Type: Application
Filed: Oct 13, 2009
Publication Date: Jul 29, 2010
Applicant: STMicroelectronics Asia Pacific Pte Ltd. (Singapore)
Inventors: Yonggang JIN (Singapore), Kiyoshi Kuwabara (Zama-shi), Xavier Baraton (Singapore)
Application Number: 12/578,382
International Classification: H01L 23/495 (20060101); H01L 27/06 (20060101); H01L 21/50 (20060101);