Abstract: A capacitor includes a stack and an external electrode located on a surface of the stack. The stack includes dielectric layers and internal electrode layers alternately stacked on one another. The stack further includes intermediate layers each between a dielectric layer and an internal electrode layer. The intermediate layers contain a dielectric component of the dielectric layers and a conductive component of the internal electrode layers. Each intermediate layer has a concentration gradient in which a concentration of the conductive component decreases from a portion adjacent to the internal electrode layer to a portion adjacent to the dielectric layer.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: The invention provides a multilayer ceramic capacitor comprising a capacitor body composed by alternately layering dielectric layers and inner electrode layers. Accordingly, the multilayer ceramic capacitor has high relative permittivity and is high the temperature property and highly accelerated life test property.

Abstract: A multilayer ceramic capacitor includes a plurality of ceramic dielectric layers, a plurality of inner electrode layers and and external electrodes. The ceramic dielectric layers includes barium titanate crystal grains having pores inside. The inner electrode layers are between the ceramic dielectric layers. The external electrodes are electrically connected to the inner electrode layers. The barium titanate crystal grains each have a core-shell structure which include a core and a shell around the core. The the pores are mainly formed in the cores.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: The invention provides a multilayer ceramic capacitor comprising a capacitor body composed by alternately layering dielectric layers and inner electrode layers, and each of the above mentioned dielectric layers contains a plurality of crystal particles, and grain boundary phases comprising interfacial grain boundaries and triple point grain boundaries formed among a plurality of the crystal particles adjacent to one another, and Si—Ba—O compound being formed in 5% or more of the triple point grain boundaries in the entire triple point grain boundaries per unit surface area of the dielectric layer. Accordingly, the multilayer ceramic capacitor has high relative permittivity and is high the temperature property and highly accelerated life test property.

Abstract: A multilayer ceramic capacitor includes a plurality of ceramic dielectric layers, a plurality of inner electrode layers and and external electrodes. The ceramic dielectric layers includes barium titanate crystal grains having pores inside. The inner electrode layers are between the ceramic dielectric layers. The external electrodes are electrically connected to the inner electrode layers. The barium titanate crystal grains each have a core-shell structure which include a core and a shell around the core. The the pores are mainly formed in the cores.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: Provided is a multilayer ceramic capacitor having a capacitor body formed by alternately laminating a dielectric layer and an internal electrode layer, and an external electrode formed on both ends of the capacitor body. The dielectric layer has at least two type of barium titanate crystal grains that differ from one another in at least one selected from Ca composition concentration, Sr composition concentration, and Zr composition concentration, and a grain boundary phase. If this multilayer ceramic capacitor employs, as a dielectric layer, a dielectric ceramic that contains barium titanate crystal grains in which part of Ba is substituted by Ca, Sr, or Zr, it is capable of suppressing the grain growth of crystal grains, and improving relative dielectric constant, temperature characteristic, and high-temperature load test characteristic, for example, in high-volume manufacturing using a tunnel type large kiln.

Abstract: A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.

Abstract: Crystal grains mainly composed of barium titanate have a mean grain size of not more than 0.2 ?m. The volume per unit cell V that is represented by a product of lattice constant (a, b, c) figured out from the X-ray diffraction pattern of the crystal grains is not more than 0.0643 nm3. Thereby, a dielectric ceramics having high relative dielectric constant can be obtained. A multilayer ceramic capacitor comprises a capacitor body and an external electrode that is formed at both ends of the capacitor body. The capacitor body comprises dielectric layers composed of the dielectric ceramics, and internal electrode layers. The dielectric layers and the internal electrode layers are alternately laminated.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.

Abstract: A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.