Abstract: A nonvolatile semiconductor memory device having a redundancy memory cell MC-R and a memory cell MC-C.sub.0 for storing relief data for designating a memory cells MC for which the memory cell MC-R is substituted. In writing the relief data, the memory cell MC-C.sub.0 is selected by a relief bit selection circuit RSEL. The relief data that is written is initially loaded in relief data latch CLAT by the instruction of a reset signal MD2. In normal writing and reading operations, the address comparator circuit ACMP compares the relief data with the address data fed from an external unit. When they are in agreement, the redundancy memory cell MC-R is selected.

Abstract: A plurality of memory cells have their sources and drains formed integrally with n.sup.+ -buried layers acting as first data lines in a semiconductor substrate. The n.sup.+ -buried layers are connected with second data lines through transfer MISFETs. These transfer MISFETs have their gates made of the same layer of polycrystalline silicon as that of the floating gates of memory cells and are shunted at each predetermined number of bits by Al lines having a lower resistance than that of the polycrystalline silicon.

Abstract: A microcomputer mounted on a single semiconductor chip includes a central processing unit and a nonvolatile flash memory which allows the information to be processed by the central processing unit to be re-programmed by electrical erasing and programming operations. The microcomputer is provided with a normal power supply voltage terminal and a programming power supply voltage terminal and also incorporates a power supply voltage level detection device and an internal voltage boost circuit to decide the re-programming mode for the flash memory according to the level of the voltage supplied and to select between the boost voltage and the external high voltage in performing the erasing and programming of data.

Abstract: A single chip type microcomputer includes at least a central processing unit (CPU), a random-access memory (RAM), a mask read-only memory (mask ROM) and an electrically writable ROM such as an electrically erasable and programamble read-only memory (EEP-ROM). The electrically writable ROM stores both the user program and data to be preserved. The microcomputer includes further memory for storing a write control program for controlling the write operation to the writable ROM, and the electrically writable ROM and the memory are disposed to mutually different address positions on the address space of CPU. The proportion of size of the user program region and the data region in the writable ROM can be selected in a free proportion. A timer governs writes to the writable ROM.

Abstract: A single chip type microcomputer includes at least a central processing unit (CPU), a random-access memory (RAM), a mask read-only memory (mask ROM) and an electrically writable ROM such as an electrically erasable and programmable read-only memory (EEP-ROM). The electrically writable ROM stores both the user program and data to be preserved. The microcomputer includes further memory for storing a write control program for controlling the write operation to the writable ROM, and the electrically writable ROM and the memory are disposed to mutually different address positions on the address space of CPU. The proportion of size of the user program region and the data region in the writable ROM can be selected in a free proportion. A timer governs writes to the writable ROM.

Abstract: Easy testability and data security of an electrically erasable programmable read only memory (EEPROM) can be accomplished by disposing pads and an input/output (I/O) circuit providing addresses, data and control signals necessary for the EEPROM test on a semiconductor substrate and by disposing a two-level test I/O interception circuit consisting of an EEPROM device on the substrate such that once the testing is completed, unauthorized accessing is prevented from outside the semiconductor substrate as a result of having a built-in data security function. A microcomputer having this capability is provided with a central processing unit (CPU) for processing data, a memory, such as an EEPROM, which is internally communicating through a common bus (which transmits data, address and control signals) with the CPU, other than during a test mode, and first and second inhibition circuits which provide the security.

Abstract: A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.

Abstract: A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.

Abstract: A data processing LSI constructing a microcomputer has an EPROM for changing a program. The EPROM can be accessed directly through the external terminals of the data processing LSI. The EPROM is statically operated when it is written with data by direct access. However, the statically operated EPROM consumes relatively high power. This power consumption by the EPROM is reduced by dynamically operating its read circuit, address decoder and so on. For example, the read circuit is constructed of a sense amplifier and a latch circuit, and the sense amplifier has its operation interrupted after the latch circuit has latched the read data. The address decoder is composed of a load MOSFET and address MOSFETs. The load MOSFET is caused to act as a precharge element in the dynamic operation and as an operation current feeding element in the static operation.

Abstract: A semiconductor integrated circuit device which inhibits the output of programmed data of its built-in memory to external terminals but outputs the result of a comparison of the programmed data with an input signal supplied from a first external terminal to a second external terminal.

Abstract: The present invention relates to a semiconductor device and a process for producing the same. The principal surface of a semiconductor pellet is provided with a plurality of first bonding pad electrodes arranged in a first arrangement state and a plurality of second bonding pad electrodes which are provided with substantially the same electric circuit functions as those of the corresponding first bonding pad electrodes and which are arranged in a second arrangement state that is different from the first arrangement state. By virtue of the above-described means, it is possible to connect together pad electrodes and mating external terminals of a mounting substrate in the same way regardless of whether the pellet is mounted according to the face-up or face-down method.

Abstract: A data processing LSI constructing a microcomputer has an EPROM for changing a program. The EPROM can be accessed directly through the external terminals of the data processing LSI. The EPROM is statically operated when it is written with data by direct access. However, the statically operated EPROM consumes relatively high power. This power consumption by the EPROM is reduced by dynamically operating its read circuit, address decoder and so on. For example, the read circuit is constructed of a sense amplifier and a latch circuit, and the sense amplifier has its operation interrupted after the latch circuit has latched the read data. The address decoder is composed of a load MOSFET and address MOSFETs. The load MOSFET is caused to act as a precharge element in the dynamic operation and as an opertion current feeding element in the static operation.

Abstract: A semiconductor integrated circuit device which inhibits the output of programmed data of its built-in memory to external terminals but outputs the result of a comparison of the programmed data with an input signal supplied from a first external terminal to a second external terminal.

Abstract: In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first inverter and which is also constructed of CMOS field effect transistors, the supply of clock signals to the first inverter is stopped in response to a particular microinstruction. After the supply of clock signals is stopped, the output voltage of the first inverter is clamped to a predetermined value, thus reducing the power dissipation in the dynamic CMOS circuit and also preventing the deterioration of data during the stopping of clock signals.

Abstract: An analog data acquisition device fetches a plurality of analog data by a multiplexer in time-division, compares the analog data fetched with a reference value applied from a digital-to-analog converter by a two-input comparator, and produces the result of comparison to a data bus. The result of comparison is also applied to a successive approximation register where the analong-to-digital conversion is effected by successively changing the digital data to the digital-to-analog converter, and the digital data converted is read out onto the data bus.The digital data applied to the digital-to-analog converter is either the output from the successive approximation register or the output from the reference register loaded through the data bus, in accordance with the contents of the control register loaded through the data bus. Thus, in which mode the device operates, in the comparing mode or in the analog-to-digital conversion mode, is selected by the control register.

Abstract: A process for manufacturing high-resilient flexible urethan foams characterized by, reacting and foaming polyalkylene ether polyol and an organic polyisocyanate in the presence of a blowing agent, a surfactant and catalyst, (1) using as said polyalkylene ether polyol one which contains 2 to 10% by weight of a vinyl type polymer and in which its hydroxyl number ranges from 25 to 60 mg KOH/g, of its hydroxyl groups 20 to 70 mol% are primary hydroxyl groups and the remaining hydroxyl groups are secondary hydroxyl groups; (2) using as said organic polyisocyanate a mixture of tolylene diisocyanate with diphenylmethane diisocyanate or a crude diphenylmethane diisocyanate; and (3) using as said surfactant a mixture of a high-molecular-weight siloxane-oxyalkylene copolymer with a low-molecular-weight siloxane-oxyalkylene copolymer.

Abstract: In ionization electrostatic plating, a cathode is incorporated separately of the article subjected to plating which has conventionally been adapted to function as makeshift cathode. The electric circuit to said article is designed to permit flow of electric current which is wholly consumed for heating the article to a temperature required for plating, so that the article will no longer play the main part of a cathode for glow discharge.This method prevents the film of plating material deposited on the article from breaking, heightens the plating efficiency and, consequently, provides highly desirable plating of metal and also non-metal articles.